Through-Via Package Structure for 3D Interconnect Yield
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Solution Overview
Problem
The semiconductor industry faces challenges in efficiently forming package structures for 3D integrated circuits and wafer-level packages, particularly in achieving reliable electrical connections and minimizing packaging defects, which affects integration density and yield.
Innovation Solution
A method involving the formation of a dielectric layer with redistribution lines, semiconductor devices, molding compound, and through-via interconnects, where conductors are formed using metal-paste printing and laser drilling to create tapered openings and connections, allowing for electrical connectivity and improved topography control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional packaging methods are used for 3D integrated circuits, then manufacturing simplicity is maintained, but integration density and yield are reduced
Solution Approach 1:
The patent transitions from conventional 2D packaging to 3D packaging by forming vertical through-vias that penetrate through the molding compound and dielectric layers, enabling electrical connections in the third dimension. This allows multiple semiconductor devices to be stacked and interconnected vertically, significantly increasing integration density while managing the complexity through systematic via formation processes
Solution Approach 2:
The patent implements nested structures where through-vias are formed within the molding compound and dielectric layers, creating concentric layers of interconnect structures. The through-vias are nested within the package structure, with conductive material filled inside the via openings, forming a nested configuration that enables complex 3D interconnections while maintaining manufacturing feasibility
2Reliability
If through-via interconnects are formed in molding compound and dielectric layers, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming openings in the dielectric layer and molding compound before filling them with conductive material. The openings are pre-formed with appropriate dimensions and positions, and the conductive material is subsequently filled into these pre-prepared openings, ensuring reliable electrical connections while simplifying the overall manufacturing process through staged fabrication
Solution Approach 2:
The patent replaces conventional mechanical drilling or punching methods with laser drilling to form openings in the molding compound and dielectric layers. This substitution enables precise control of via dimensions, cleaner opening formation, and better integration with subsequent filling processes, improving both electrical connection reliability and manufacturing ease
3Manufacturing precision
If laser drilling is used to form tapered openings, then manufacturing precision is improved, but energy consumption increases
Solution Approach 1:
The patent utilizes laser drilling with controlled parameters to form tapered openings in the dielectric layer and molding compound. By adjusting laser power, pulse duration, and scanning speed, the process achieves precise control over opening dimensions and taper angles, ensuring high manufacturing precision while optimizing energy consumption through parameter optimization rather than excessive energy input
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density and yield of semiconductor packages by ensuring reliable electrical connections and minimizing defects, facilitating the formation of complex 3D structures with improved topography control.
Implementation Method 1
conformal coatings are deposited over the semiconductor devices and the molding compound. Tapered openings are drilled through the dielectric layer and the molding compound using a laser.
Data Source
AI summary
A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.


