Through-Via Pad Structure for Dense Reliable Semiconductor Packaging
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Solution Overview
Problem
Current semiconductor packages face challenges in increasing integration density and speed while maintaining reliability, particularly in the design and manufacturing of semiconductor chips with through vias and pads.
Innovation Solution
The semiconductor chip design includes a semiconductor substrate with through vias and upper pads, where the pads surround the vias and at least one pad has a tetragonal cross-sectional shape, enhancing electrical connectivity and reliability. Additionally, the semiconductor package incorporates a high bandwidth memory control die and dynamic random-access memory dies with specific coupling pads and insulation layers for improved signal transfer and heat management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional pad designs are used in semiconductor chips, then manufacturing is simpler, but electrical connectivity and reliability are reduced
Solution Approach 1:
The pad structure is designed to surround the through via, creating a nested configuration where the pad encircles the via. This nested doll principle enhances electrical connectivity by providing multiple contact paths while maintaining a compact structure that does not significantly increase overall device complexity.
Solution Approach 2:
At least one pad is designed with a tetragonal cross-sectional shape rather than a conventional circular or square shape. This asymmetric geometry optimizes the pad's electrical field distribution and contact area with the through via, improving reliability while the specific geometric form factor keeps manufacturing within reasonable complexity bounds.
2Productivity
If integration density is increased to improve performance, then speed and capacity improve, but reliability may deteriorate
Solution Approach 1:
The nested pad-via structure allows for more efficient space utilization, enabling higher integration density without proportionally increasing the risk to reliability. The surrounding pad configuration provides redundant electrical pathways that maintain reliability even as density increases.
Solution Approach 2:
The pad structure is optimized locally at each via location with the surrounding configuration and tetragonal cross-section, providing enhanced electrical connectivity at critical points. This localized quality improvement ensures reliability is maintained in high-density regions where electrical connections are most critical.
3Reliability
If conventional through via and pad configurations are used, then device complexity is lower, but electrical connectivity and thermal management are insufficient
Solution Approach 1:
The pad surrounds the through via in a nested configuration, creating multiple electrical contact points between the pad and via. This nested structure improves electrical connectivity by providing redundant pathways while the compact nested form factor limits the increase in overall device complexity.
Solution Approach 2:
The tetragonal cross-sectional shape of at least one pad creates an asymmetric electrical field distribution that optimizes contact with the circular via. This geometric asymmetry improves electrical connectivity and thermal management efficiency without adding significant manufacturing complexity compared to conventional symmetric pad designs.
Data Source
AI summary
A semiconductor chip includes a semiconductor substrate, a plurality of through vias passing through at least a portion of the semiconductor substrate, and a plurality of upper pads contacting the plurality of through vias, wherein, in a plan view, each of the plurality of upper pads surrounds a respective one of the plurality of through vias, and at least one of the plurality of upper pads has a tetragonal cross-sectional shape.