Through-Via Conductive Pad Structure for Peel Stress Relief
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Challenges in 3DICs include peeling issues between through vias and dielectric materials due to peel stress, which affect the integrity and reliability of the semiconductor package.
Innovation Solution
Incorporation of dielectric patterns or holes within the conductive pad over the through via to reduce conductor density and alleviate peel stress, enhancing the bonding between the through via and dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through vias are formed in substrate to create 3DIC structure, then integration density and bandwidth are improved, but peel stress causes bonding integrity to deteriorate
Solution Approach 1:
The patent applies porous dielectric materials within the conductive pad structure to reduce conductor density and alleviate peel stress. The porous structure allows stress relief while maintaining electrical connectivity, directly addressing the bonding integrity issue in 3DIC through vias
Solution Approach 2:
The patent uses composite material structures combining conductive and dielectric materials in a layered configuration within the conductive pad. This composite approach distributes stress more effectively and prevents peeling between through vias and dielectric layers
2Reliability
If conductor density is increased in conductive pad, then electrical connectivity is improved, but peel stress increases causing bonding to deteriorate
Solution Approach 1:
The patent applies local quality by creating regions of varying conductor density within the conductive pad. Areas with higher electrical demand have increased conductor density, while other regions use dielectric patterns to reduce peel stress, optimizing both connectivity and bonding strength locally
Solution Approach 2:
Porous dielectric materials are strategically placed within the conductive pad to reduce overall conductor density while maintaining necessary electrical connectivity. The porous structure provides stress relief pathways that prevent bonding deterioration
3Strength
If dielectric patterns are added within conductive pad, then peel stress is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the conductive pad into distinct regions with dielectric patterns, allowing independent optimization of stress resistance in specific areas. This segmentation enables targeted stress management without requiring complete redesign of the entire pad structure
Solution Approach 2:
The dielectric patterns are nested within the conductive pad structure, with dielectric regions embedded in the conductive material. This nested configuration allows stress relief features to be integrated without adding external structural complexity
Data Source
AI summary
A method of forming an integrated circuit comprises the following steps. A through via is formed in a substrate. A dielectric layer is formed over the through via. The dielectric layer is patterned to form a first hole and at least one dielectric pattern in the first hole. A conductive pad is formed in the first hole to surround the at least one dielectric pattern and electrically connect to the through via.