Through-Substrate Via Power Network for Scaled MOSFET Integration
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Solution Overview
Problem
As semiconductor devices continue to scale down, the characteristics of MOSFETs degrade, leading to performance limitations due to increased integration.
Innovation Solution
A semiconductor device design incorporating a substrate with active patterns, device isolation layers, stacked patterns, and through vias that penetrate active and isolation layers, enhancing power transmission and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET size is scaled down to increase integration, then device density increases, but device characteristics degrade
Solution Approach 1:
The patent introduces a vertical power transmission network with through-vias penetrating multiple layers (substrate, device isolation layer, stacked pattern) to establish three-dimensional power distribution. This vertical dimension complements the scaled-down horizontal device layout, enabling efficient power delivery despite reduced device footprint and maintaining device characteristics through optimized power supply architecture.
Solution Approach 2:
The power transmission network is segmented into multiple components: power transmission network layer on substrate, through-vias penetrating device isolation layer and stacked pattern, and interconnected power transmission paths. This segmentation allows independent optimization of each component while achieving overall efficient power distribution to support scaled-down MOSFETs.
2Productivity
If device size is reduced, then device density increases, but power transmission efficiency decreases
Solution Approach 1:
The patent implements a three-dimensional power transmission architecture with vertical through-vias and multi-layer power networks. This vertical power delivery path reduces horizontal current flow distance and resistance, maintaining power transmission efficiency even as horizontal device dimensions are reduced to increase density.
Solution Approach 2:
The through-vias and power transmission network layer act as intermediaries between power sources and scaled-down devices. These intermediary structures provide dedicated power transmission pathways that compensate for the reduced device size, ensuring efficient energy delivery without direct contact between power sources and miniaturized devices.
3Ease of operation
If through via penetrates deep into substrate, then power transmission reaches lower layers, but manufacturing complexity increases
Solution Approach 1:
The deep through-via is segmented into multiple sections: first through via penetrating substrate and device isolation layer, second through via penetrating stacked pattern, with intermediate connection structures. This segmentation breaks down the complex single via into manageable sections that can be manufactured using standard multi-step via formation processes, reducing overall manufacturing complexity.
Solution Approach 2:
The patent forms preliminary via structures (first through via, second through via) in separate manufacturing steps before final interconnection. This preliminary action allows each via section to be optimized and formed independently using established processes, simplifying the overall manufacturing of the complete deep via structure.
Data Source
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AI summary
A semiconductor device includes: a substrate including active patterns; a device isolation layer disposed between the active patterns; a stacked pattern disposed on the substrate; a power transmission network layer disposed on a first surface of the substrate; a first through via penetrating the stacked pattern; and a second through via disposed between the power transmission network layer and the first through via, wherein the second through via penetrates the active patterns and the device isolation layer.