Through-Via Power Delivery Layout for Stacked Chips With Lower RC Delay
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Solution Overview
Problem
Existing power delivery structures for stacked integrated circuits (ICs) in advanced IC packages are inadequate in reducing resistance-capacitance (RC) delay, power delivery efficiency, and chip area utilization, and lack design flexibility due to constraints on through via pitch.
Innovation Solution
The implementation of through via power delivery structures that directly connect to each chip in a stacked chip structure, eliminating intermediate connections and allowing for independent power delivery TSVs with dedicated guard rings, reducing RC delay and optimizing chip area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional power delivery structures with intermediate connections are used, then manufacturing constraints are simplified, but RC delay increases and power delivery efficiency decreases
Solution Approach 1:
The patent extracts and eliminates the intermediate connection structures from the power delivery path. Through vias are configured to directly connect to contact holes in the chip, removing the intermediate bonding pads and wire bonds that previously existed in traditional power delivery structures. This extraction reduces the number of connection interfaces and minimizes RC delay.
Solution Approach 2:
The patent transitions from a planar power delivery architecture to a three-dimensional vertical architecture. Power delivery moves from horizontal routing through intermediate connections to vertical through-via connections that penetrate through the substrate, enabling direct access to contact holes in the chip and reducing the power delivery path length.
2Adaptability or versatility
If through via pitch is constrained by chip bonding pitch, then manufacturing is simplified, but design flexibility and area utilization decrease
Solution Approach 1:
The patent segments the through via pitch requirements from the chip bonding pitch requirements. By introducing independent via pitch parameters that are not tied to the bonding pitch, the design allows for optimized via spacing that is determined by electrical performance requirements rather than manufacturing constraints, enabling independent optimization of both aspects.
Solution Approach 2:
The patent introduces dynamic flexibility in via pitch selection, allowing the via pitch to be independently adjusted based on electrical performance requirements such as RC delay minimization and area utilization optimization, rather than being fixed by manufacturing bonding pitch constraints.
3Manufacturing precision
If intermediate connections are used for power delivery, then manufacturing precision requirements are reduced, but power delivery efficiency and RC delay performance worsen
Solution Approach 1:
The patent extracts and removes the intermediate connection layers (bonding pads, wire bonds, and associated interconnect structures) from the power delivery path. This eliminates multiple alignment interfaces that would require precise manufacturing tolerances, replacing them with direct through-via-to-contact-hole connections that reduce the number of critical alignment steps.
Solution Approach 2:
The patent transitions from a multi-layer planar connection architecture to a vertical through-substrate connection architecture. This dimensional change reduces the number of lateral alignment steps required and minimizes the total connection path length, thereby reducing RC delay while maintaining manufacturing feasibility.
4Area of stationary object
If through via dimensions are tethered to chip bonding pitches, then manufacturing is simplified, but area utilization and power delivery performance decrease
Solution Approach 1:
The patent segments via dimension specifications from bonding pitch specifications, allowing via diameter, length, and spacing to be independently optimized for electrical performance and area utilization rather than being constrained by manufacturing bonding pitch requirements.
Solution Approach 2:
The patent enables independent variation of via dimensional parameters (diameter, length, spacing) from bonding pitch parameters, allowing optimization of via dimensions based on electrical performance requirements such as current carrying capacity, RC delay, and area utilization without being constrained by fixed manufacturing pitch requirements.
Data Source
AI summary
Through via power delivery structures for chip stacks and methods of fabrication thereof are disclosed. An exemplary stacked chip structure includes a first chip and a second chip. The first chip has a first substrate, a first device layer, and a first interconnect structure. The second chip has a second substrate, a second device layer, and a second interconnect structure. A first through via extends through the first substrate, the first device layer, the first interconnect structure, and into the second interconnect structure. A second through via extends through the first substrate, the first device layer, and into the first interconnect structure. The second through via and the first through via may be electrically connected to the first device layer and the second device layer, respectively, and power may be delivered to the first device layer and the second device layer via the second through via and the first through via, respectively.