Through Via Protrusion for Short Circuit Prevention
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Solution Overview
Problem
Conventional silicon chips with through vias face issues due to the limitations of the passivation layer patterning process, which often results in either short circuits or complex, costly high-resolution processes, as the diameter of the opening in the passivation layer is either too small or too large, leading to direct contact with the silicon substrate.
Innovation Solution
A method involving the exposure of the first end of the through via to the passivation layer surface, allowing for a lower resolution process without short circuits, by removing part of the silicon substrate and forming a passivation layer that covers the through via, followed by partial removal to expose the via end, enabling a redistribution layer to connect without contacting the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the passivation layer is patterned by a high resolution process to ensure the opening diameter is smaller than the through hole diameter, then short circuits are avoided, but the manufacturing process becomes complex and costly
Solution Approach 1:
The through via is made to protrude through the passivation layer before final patterning, ensuring proper exposure in advance. This preliminary positioning eliminates the need for high-resolution patterning to control the opening size, as the via protrusion geometry inherently prevents short circuits while allowing standard-resolution patterning processes to be used.
2Ease of manufacture
If the passivation layer opening diameter is made larger for easier manufacturing, then the patterning process is simplified, but the redistribution layer directly contacts the silicon substrate causing short circuits
Solution Approach 1:
The solution moves from controlling only the horizontal opening diameter to incorporating vertical dimension control. The through via protrudes through the passivation layer by a controlled height, creating a three-dimensional structure where the via extends above the passivation layer surface. This vertical protrusion ensures that even with larger opening diameters from lower-resolution patterning, the via remains exposed and connected to the redistribution layer without shorting to the substrate.
3Reliability
If the passivation layer opening diameter is made smaller to prevent substrate contact, then short circuits are avoided, but the patterning process requires high resolution which increases cost
Solution Approach 1:
The through via is formed to protrude through the passivation layer in advance of the final patterning step. This preliminary via protrusion structure ensures that the via endpoint is already positioned correctly above the passivation layer, eliminating the need for high-resolution patterning to achieve precise opening sizes. Standard-resolution processes can then be used to form the opening, reducing manufacturing cost while maintaining reliability.
Data Source
AI summary
The present invention relates to a silicon chip having a through via and a method for making the same. The silicon chip includes a silicon substrate, a passivation layer, at least one electrical device and at least one through via. The passivation layer is disposed on a first surface of the silicon substrate. The electrical device is disposed in the silicon substrate, and exposed to a second surface of the silicon substrate. The through via includes a barrier layer and a conductor, and penetrates the silicon substrate and the passivation layer. A first end of the through via is exposed to the surface of the passivation layer, and a second end of the through via connects the electrical device. When a redistribution layer is formed on the surface of the passivation layer, the redistribution layer will not contact the silicon substrate, thus avoiding a short circuit. Therefore, a lower resolution process can be used, which results in low manufacturing cost and simple manufacturing process.