Through-Via Layout for Resistance Tuning in Semiconductor Stacks
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Solution Overview
Problem
Semiconductor devices with through via structures face challenges in adjusting resistance and preventing the reduction of electrical performance of integrated circuit layers, particularly when these structures are used as electrodes and are integrated near transistors.
Innovation Solution
The semiconductor device incorporates multiple through via structures with varying diameters and heights, strategically positioned apart from the integrated circuit layer, allowing for adjustable resistance and mitigating performance reduction by optimizing the separation distances and connection points within the device's wiring layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through via structures are used as electrodes with fine holes in semiconductor devices, then data processing capacity and bandwidth are improved, but resistance adjustment becomes difficult and electrical performance of integrated circuit layers is reduced
Solution Approach 1:
The patent applies local quality by varying the diameters of different through via structures (first through via structure has first diameter, second through via structure has second diameter) and positioning them at different distances from the integrated circuit layer. This allows each through via structure to have optimized electrical characteristics suitable for its specific function and location, resolving the contradiction between achieving low resistance for high bandwidth and maintaining electrical performance near sensitive circuit elements.
2Reliability
If through via structures are positioned near integrated circuit layers to reduce resistance, then electrical connection efficiency is improved, but electrical performance of the integrated circuit layer is degraded
Solution Approach 1:
The patent changes the parameter of separation distance between through via structures and the integrated circuit layer. By optimizing this distance parameter, the patent achieves a balance where through via structures are close enough to provide low-resistance electrical connections but far enough to avoid degrading the electrical performance of the integrated circuit layer.
Solution Approach 2:
Different through via structures are positioned at different local positions relative to the integrated circuit layer, with some closer for low resistance and others farther for performance protection, allowing localized optimization of electrical characteristics.
Data Source
AI summary
A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.