Through-Substrate Via Formation Using Sacrificial FEOL Features

Solution Overview

Problem

Existing through-silicon via (TSV) structures face challenges in pattern uniformity and processing consistency due to large area coverage and differing pattern densities, leading to issues like dishing during chemical mechanical polishing in integrated circuit fabrication.

Innovation Solution

The method involves forming sacrificial features in the through via region during the front-end-of-the-line (FEOL) processes, allowing for concurrent formation of active device features and through vias, which improves pattern uniformity and reduces processing challenges such as dishing by forming dummy gate structures, source/drain features, and replacing them with metal gates, ensuring consistent processing across the substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If through-silicon via (TSV) structures are formed with large area coverage, then routing capability is improved, but pattern uniformity deteriorates due to differing pattern densities

Engineering Contradiction:

Improvearea coverage of TSVVSAvoidpattern uniformity

Core Design Contradiction:

Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent applies local quality by forming dummy features specifically in the through via region where pattern density differs from active device regions. These dummy features (dummy gates, source/drain features, channel features) are placed only in areas needing pattern density compensation, not uniformly across the entire substrate. This localized approach maintains pattern uniformity in the TSV region while preserving the functionality of active device regions.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements preliminary action by forming dummy features during the front-end-of-line (FEOL) processes, concurrent with active device feature formation, rather than adding them later. The dummy features are formed before the through via etching and filling processes, ensuring that pattern density is equalized before subsequent processing steps that would be affected by density variations.

Inventive Principle:

Principle #10Preliminary action

2Area of stationary object

If through-silicon via (TSV) structures are formed with large area coverage, then routing capability is improved, but processing consistency deteriorates leading to dishing during chemical mechanical polishing

Engineering Contradiction:

Improvearea coverage of TSVVSAvoidprocessing consistency

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent applies local quality by forming dummy features specifically in the through via region where pattern density differs from active device regions. These dummy features (dummy gates, source/drain features, channel features) are placed only in areas needing pattern density compensation, not uniformly across the entire substrate. This localized approach maintains pattern uniformity in the TSV region while preserving the functionality of active device regions.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements preliminary action by forming dummy features during the front-end-of-line (FEOL) processes, concurrent with active device feature formation, rather than adding them later. The dummy features are formed before the through via etching and filling processes, ensuring that pattern density is equalized before subsequent processing steps that would be affected by density variations.

Inventive Principle:

Principle #10Preliminary action

3Manufacturing precision

If sacrificial features are formed during FEOL processes, then pattern uniformity is improved, but device complexity increases

Engineering Contradiction:

Improvepattern uniformityVSAvoidprocessing steps

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies merging by combining the formation of dummy features with the formation of active device features into a single set of FEOL processing steps. The same photolithography, etching, and deposition processes that create active device structures also create the dummy features in the through via regions. This consolidation adds minimal processing complexity while achieving pattern uniformity across the substrate.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent applies universality by designing dummy features that mirror the structure and material composition of active device features. The dummy gates, source/drain features, and channel features use the same materials and formation processes as their active device counterparts, allowing a single set of FEOL processes to serve both functional device creation and pattern density equalization purposes.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240395619A1Semiconductor device having through via and method of fabricating thereof

Publication Date: 2024.11.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Semiconductor structures and methods for forming the same that include a through substrate via. Sacrificial semiconductor structures (e.g., fins) are formed with metal gate structures in a through via region. An opening is formed through BEOL layers to expose the metal gates, which may then be removed. A liner layer is formed on sidewalls of the opening including on semiconductor structures extending from the substrate. The opening is then extended into the substrate and a through substrate via is formed from the extended opening.