Through-Via Scallop Profiling for Conductivity and Shielding

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Solution Overview

Problem

As semiconductor devices continue to integrate more components into smaller areas, the reduction in minimum feature sizes leads to challenges in controlling conductivity and requiring additional deposition and etching steps, which increases complexity and cost.

Innovation Solution

The use of a two-stage patterning process to create through vias with different scallop depths in the sidewalls, allowing for controlled conductivity without additional steps by depositing a metal layer that is continuous in one region and discontinuous in another, providing shielding and electrostatic discharge protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If additional deposition and etching steps are used to control conductivity, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improveconductivity controlVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating different scallop depths at different locations within the same through via. The sidewalls have varying scallop depths (first scallops with first depth, second scallops with second depth greater than first depth) to achieve different conductivity characteristics in different regions. This allows conductivity control without additional deposition steps, as the metal layer naturally forms different conductivity regions based on the scallop depth variations.

Inventive Principle:
Principle #3Local quality

2Reliability

If additional deposition and etching steps are used to create shielding, then shielding effectiveness is improved, but manufacturing cost increases

Engineering Contradiction:
Improveshielding effectivenessVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the shielding function with the existing through via structure by creating discontinuous metal layers in specific regions. The metal layer is made discontinuous in regions where shielding is needed, while remaining continuous in regions requiring conductivity. This integration of shielding functionality into the via structure eliminates the need for separate shielding deposition steps, reducing manufacturing cost while maintaining shielding effectiveness.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If minimum feature sizes are reduced to increase integration density, then productivity is improved, but manufacturing precision deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidfeature size control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent employs periodic action through iterative etching processes that create scallops on the sidewalls of through vias. Multiple etching iterations form a series of scallop features with controlled depths, allowing precise control of the via geometry even at reduced feature sizes. This periodic etching approach enables accurate feature size control while maintaining high integration density.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the manufacturing process by controlling conductivity and shielding without additional deposition and etching steps, reducing costs and improving integration density in semiconductor devices.

Implementation Method 1

etching a substrate with a first patterning process to form an opening in the substrate... etching the substrate with a second patterning process to extend the opening

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

depositing a metal layer in the through vias... a metal layer is then deposited in the through vias

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS11776881B2Semiconductor device and method
Publication Date: 2023.10.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11776881B2 patent drawing
  • US11776881B2 patent drawing
  • US11776881B2 patent drawing

AI summary

A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.