Through Via Manufacturing for 3D Stacked Semiconductor Packages
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Solution Overview
Problem
The miniaturization and lightweight trend in electronic products lead to signal delays and performance limitations in semiconductor devices due to increased wire lengths in stacked packages, which the existing through-substrate via (TSV) method aims to address by enabling 3D stacking and high-performance system-in-package (SIP) solutions.
Innovation Solution
A method of manufacturing semiconductor devices and packages that involves forming buried vias, planarizing substrate surfaces to create through vias, forming conductive capping layers, and recessing the substrates to extend the vias beyond the surface, improving connection performance and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional TSV method is used to enable 3D stacking, then device integration density is improved, but manufacturing precision and uniformity of through vias deteriorate
Solution Approach 1:
The through via formation process is segmented into multiple stages: first forming buried vias with initial conductive material, then planarizing the surface, and finally forming additional conductive material to complete the through via. This segmentation allows each stage to be optimized independently, improving overall precision and uniformity while maintaining high integration density.
Solution Approach 2:
The method performs preliminary planarization of the substrate surface before completing the through via formation. This preliminary action ensures that the subsequent conductive material deposition occurs on a uniform surface, thereby improving the precision and uniformity of the final through via structure while enabling 3D stacking.
2Adaptability or versatility
If wire length is increased in stacked packages, then device functionality is improved, but signal delay increases
Solution Approach 1:
The patent transitions from planar wire connections to three-dimensional through via connections by stacking semiconductor substrates vertically. This dimensional change reduces the effective signal path length despite increased device functionality, as signals travel through vertical via paths rather than long horizontal wire routes, thereby reducing signal delay.
3Ease of manufacture
If through vias are formed without planarization, then manufacturing complexity is reduced, but connection performance deteriorates
Solution Approach 1:
The planarization step extracts and removes surface irregularities from the substrate before completing the through via formation. By separating this surface preparation step from the via formation process, the method ensures uniform connection surfaces without significantly increasing overall manufacturing complexity, thereby improving connection performance.
Data Source
AI summary
A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.