Through Via Fabrication for Semiconductor Device Reliability
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Solution Overview
Problem
Conventional methods for fabricating semiconductor devices with through vias face challenges in reducing scribe lane width due to difficulties in connecting I/O pads at the chip's central region, leading to long redistributed interconnections that can cause malfunction due to parasitic capacitance or inductance, and result in electrical shorts from silicon splash during hole formation.
Innovation Solution
A method involving the formation of a first hole in the insulating layer that penetrates the I/O pad and a second hole extending into the wafer, with multi-layered and single-layered insulating layers on the inner walls, allowing for a conductive via that protrudes from the wafer's inactive surface, reducing the risk of electrical shorts and enabling efficient electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through vias are formed in scribe lanes to connect I/O pads, then electrical connection between chips is achieved, but scribe lane width cannot be reduced when I/O pads are at central region
Solution Approach 1:
The hole formation process is segmented into multiple stages: first forming a hole through the insulating layer, then extending it into the wafer. This segmentation allows for controlled progression and prevents premature silicon splash that would cause electrical shorts.
Solution Approach 2:
The insulating layer is formed and extended to the central region before hole formation begins. This preliminary action creates a protective barrier that prevents silicon splash from causing electrical shorts between the pad and wafer during the subsequent hole formation process.
2Productivity
If scribe lane width is reduced to increase chip density, then more chips fit on wafer, but electrical shorts occur due to silicon splash during hole formation
Solution Approach 1:
The insulating layer is formed and extended to the central region before hole formation begins. This preliminary action creates a protective barrier that prevents silicon splash from causing electrical shorts between the pad and wafer during the subsequent hole formation process.
Solution Approach 2:
The insulating layer acts as an intermediary material between the conductive pad and the wafer. During hole formation, this intermediary layer prevents direct electrical contact between silicon particles and the pad, eliminating the harmful effect of silicon splash.
3Ease of operation
If I/O pads are at central region for optimal layout, then device performance improves, but long redistributed interconnections cause parasitic capacitance and inductance
Solution Approach 1:
The solution moves the connection path from a planar (2D) layout to a three-dimensional (3D) structure by forming vertical through vias. This dimensional change allows I/O pads to be located at the central region while achieving direct electrical connection through the wafer thickness, eliminating long horizontal interconnections and their associated parasitic effects.
Data Source
AI summary
A method of fabricating a semiconductor device is provided. The method may include forming an insulating layer on a wafer. The wafer may have an active surface and an inactive surface which face each other, and the insulating layer may be formed on the active surface. A pad may be formed on the insulating layer, and a first hole may be formed in the insulating layer. A first hole insulating layer may then be formed on an inner wall of the first hole. A second hole may be formed under the first hole. The second hole may be formed to extend from the first hole into the wafer. A second hole insulating layer may be formed on an inner wall of the second hole. The semiconductor device fabricated according to the method may also be provided.