Through-Via Redistribution Layers for Die-Stack Thermal Routing
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Solution Overview
Problem
Semiconductor devices with multiple dies in a single package face challenges in thermal regulation due to heat generation, leading to poor thermal dissipation and reduced connectivity options, as high-heat-producing dies are often positioned at the bottom, limiting circuit area and increasing routing complexity.
Innovation Solution
A semiconductor device assembly with a through via between redistribution layers, allowing connectivity to the top semiconductor die without using limited circuit area on lower dies, by implementing a stack of semiconductor dies with a gap fill and multiple redistribution layers, enabling efficient thermal dissipation and connectivity through external components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If high-heat-producing dies are positioned at the bottom of the package, then connectivity to external terminals is improved, but thermal dissipation deteriorates and circuit area on lower dies is limited
Solution Approach 1:
The patent introduces through vias that extend vertically through the package structure, utilizing the third dimension (vertical depth) to create new interconnection paths. This allows connectivity to be achieved through the vertical dimension rather than being constrained to horizontal routing on die surfaces, thereby resolving the conflict between connectivity requirements and thermal management.
Solution Approach 2:
The package is divided into multiple functional layers with redistribution layers separating different interconnection functions. Through vias are segmented into different types (e.g., first through vias for power/ground, second through vias for signals) that serve different purposes at different vertical levels, allowing independent optimization of thermal paths and electrical connectivity.
2Ease of operation
If through vias are added to lower dies to improve connectivity, then ease of operation improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Redistribution layers are introduced as intermediary structures between the dies and external terminals. These redistribution layers provide a buffer zone for routing signals, allowing complex interconnections to be managed in discrete stages rather than requiring direct complex routing through the dies themselves. This reduces the manufacturing complexity while maintaining connectivity flexibility.
3Temperature
If circuit area on lower dies is reduced to accommodate through vias, then thermal dissipation improves, but productivity and memory capacity deteriorate
Solution Approach 1:
By moving interconnection functions to the vertical dimension through through vias and redistribution layers, the horizontal circuit area on dies is freed up. This allows more memory circuits to be placed on each die surface, increasing capacity while the vertical through via structure handles the thermal dissipation function independently.
Data Source
AI summary
A semiconductor device with a through via between redistribution layers is disclosed. The semiconductor device includes a stack of semiconductor dies coupled with first contact pads on a first redistribution layer. The first redistribution layer further includes a second contact pad located outside the footprint of the die stack and circuitry coupling the second contact pad to the first contact pads. A gap fill is disposed around the stack of semiconductor dies. A second redistribution layer is disposed at the stack of semiconductor dies and the gap fill. The second redistribution layer includes third contact pads coupled with the stack of semiconductor dies, a fourth contact pad disposed beyond the footprint of the stack of semiconductor dies, fifth contact pads opposite the third and fourth contact pads, and circuitry coupling the contact pads. A through via is disposed through the gap fill coupling the second and fourth contact pads.