Through-Via Width Control Using Variable Insulating Layer Thickness
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently manufacturing through vias with different widths, which affects the etching process and the ability to control the dimensions of via holes, leading to difficulties in filling these holes with conductive material and maintaining uniformity.
Innovation Solution
The method involves forming via holes with initially equal widths and depths, followed by the deposition of an insulating layer with varying thicknesses to create through vias of different widths, allowing for controlled expansion of one via hole while maintaining the other's dimensions, thereby reducing etching loading effects and facilitating uniform filling with conductive material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If via holes are formed with equal widths and depths, then the manufacturing process is simple, but it is difficult to create through vias with different widths required for separate data and power signal paths
Solution Approach 1:
The patent applies preliminary action by forming an insulating layer with varying thickness before via hole formation. The insulating layer is deposited with different thicknesses in different regions, and then recessed portions are removed to create via holes. This preliminary preparation of the insulating layer structure enables subsequent via holes to have different widths without requiring complex post-processing steps, thus achieving via width variation while maintaining manufacturing simplicity.
Solution Approach 2:
The patent applies local quality by creating regions with different insulating layer thicknesses at specific locations. The insulating layer has a first thickness in a first region and a second thickness in a second region, allowing each location to have the specific via width needed for its function (data or power signal). This local differentiation enables versatile via width configuration while using a relatively simple global manufacturing process.
2Manufacturing precision
If insulating layer thickness is reduced to increase via hole width, then via hole width increases for better signal paths, but etching loading effects become harder to control
Solution Approach 1:
The patent applies parameter changes by systematically varying the insulating layer thickness as a key parameter to control via hole width. Instead of trying to control via hole width directly through etching parameters, the patent changes the insulating layer thickness parameter beforehand, which then determines the via hole width after recess removal. This indirect parameter control achieves precise via hole width control while avoiding the etching loading effects that would result from direct etching control.
3Adaptability or versatility
If through vias have different widths, then separate paths for data and power signals are enabled, but uniform filling with conductive material becomes difficult
Solution Approach 1:
The patent applies preliminary action by pre-forming the insulating layer structure with varying thicknesses and removing recess portions before conductive material filling. This creates via holes with different widths that are already prepared and ready for uniform conductive filling. The preliminary structuring of the insulating layer ensures that subsequent conductive material deposition can uniformly fill each via hole according to its specific width requirements, achieving both signal path separation and filling uniformity.
Data Source
AI summary
There is provided a semiconductor device including through vias and a method of manufacturing the same. The semiconductor device includes a substrate including a first via hole and a second via hole, a first through via formed in the first via hole, a second through via formed in the second via hole, an insulating layer first portion formed between a sidewall surface of the first via hole and the first through via, and an insulating layer second portion formed between a sidewall surface of the second via hole and the second through via. The insulating layer second portion is thinner than the insulating layer first portion, and the second through via is wider than the first through via,