Through Vias in Semiconductor Substrates Reducing Parasitic Effects
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Solution Overview
Problem
Conventional through vias in semiconductor devices introduce parasitic effects due to interconnects, which degrade transistor performance by increasing inductance and capacitance, limiting the effectiveness of parasitic reduction.
Innovation Solution
The implementation of through vias extending through doped regions in semiconductor substrates, coupled with conductive layers and metallization structures, minimizes parasitic effects by reducing contact resistance and optimizing strain fields, thereby enhancing transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional through vias with interconnects are used, then electrical connection is achieved, but parasitic effects (inductance and capacitance) increase
Solution Approach 1:
The patent extracts and removes the harmful interconnect structures from the through via configuration. By eliminating the separate interconnect layers and using direct vertical conductive paths through the substrate, the design removes the source of parasitic inductance and capacitance while maintaining electrical connectivity between transistor regions.
Solution Approach 2:
The patent merges the through via formation with the substrate structure itself. Instead of adding separate interconnect layers, the conductive paths are integrated directly into the substrate, combining the substrate and interconnect functions into a single unified structure that reduces parasitic effects.
2Reliability
If through vias extend through doped regions, then contact resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary doping to the substrate regions where through vias will be formed. By pre-doping these areas before via formation, the conductive paths are prepared in advance, ensuring low contact resistance is achieved when the vias are created, while the doping process itself is integrated into the existing manufacturing flow.
Data Source
AI summary
In accordance with an embodiment of the present invention, a semiconductor chip includes a device region disposed in or over a substrate, a doped region disposed in the device region, and a through via disposed in the substrate. The through via extends through the doped region.