Through-Wafer Interconnect Using Patterned Trench
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Solution Overview
Problem
Conventional through-wafer interconnection methods are complex and lack design flexibility, with limitations in conductor thickness and shape due to electroplating techniques, resulting in rigid interconnects with high parasitic capacitance and resistance.
Innovation Solution
The method involves starting with a conductive wafer to form a through-wafer conductor by creating a patterned trench, using native material for insulation and a frame, allowing for varied shapes and sizes to minimize parasitic capacitance and enhance mechanical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional electroplating techniques are used to form through-wafer conductors, then the conductor thickness can be controlled, but the design flexibility and shape variability are limited
Solution Approach 1:
Instead of forming a conductor by depositing material into a pre-formed via (conventional approach), the patent inverts the process by first creating a patterned trench in a conductive wafer and then using the native conductive material to form the through-wafer conductor. This inversion allows the conductor shape and thickness to be directly defined by the trench geometry, providing both precise thickness control and enhanced design flexibility for varied conductor shapes and configurations.
2Reliability
If through-wafer vias are filled with connective material, then electrical connection is achieved, but parasitic capacitance and interconnection resistance increase
Solution Approach 1:
The patent changes the physical parameters of the through-wafer conductor by forming it as a patterned trench structure with controlled geometry rather than filling a via with connective material. This parameter change in the conductor formation method enables precise control of conductor cross-sectional area and path length, thereby reducing parasitic capacitance and interconnection resistance while maintaining reliable electrical connection.
3Reliability
If conventional bond pad interconnection is used, then devices can be connected to the backside, but wafer surface space is consumed
Solution Approach 1:
The patent transitions from two-dimensional surface-level bond pad interconnection to three-dimensional through-wafer interconnection by creating vertical conductive paths through the wafer thickness. This dimensional change allows electrical connection between front-side and backside devices without occupying valuable wafer surface area, as the interconnection occurs through the wafer volume rather than on the surface.
4Reliability
If long wires are routed across the wafer surface, then devices can be interconnected, but interconnection resistance and parasitic capacitance increase
Solution Approach 1:
The patent eliminates long surface-level wire routing by creating direct vertical through-wafer conductive paths. This dimensional change from horizontal surface routing to vertical through-wafer routing significantly shortens the interconnection path length, thereby reducing both interconnection resistance and parasitic capacitance while maintaining reliable device interconnection.
Data Source
AI summary
A through-wafer interconnect and a method for fabricating the same are disclosed. The method starts with a conductive wafer to form a patterned trench by removing material of the conductive wafer. The patterned trench extends in depth from the front side to the backside of the wafer, and has an annular opening generally dividing the conductive wafer into an inner portion and an outer portion whereby the inner portion of the conductive wafer is insulated from the outer portion and serves as a through-wafer conductor. A dielectric material is formed or added into the patterned trench mechanical to support and electrically insulate the through-wafer conductor. Multiple conductors can be formed in an array.