Through Wire Interconnects for Stacked Semiconductor Substrates
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Solution Overview
Problem
Conventional interconnects in semiconductor components face limitations in electrical conductivity, capacitance, density, and manufacturing, particularly for stacked semiconductor configurations, where they struggle to provide high-performance signal transmission with low parasitic capacitance and noise.
Innovation Solution
The development of through wire interconnects (TWI) that include a via through the substrate, a bonded wire, and a dielectric material, which are used to connect semiconductor substrates in stacked configurations, reducing capacitance and noise by using bonding members and dielectric insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If wire interconnects are used to electrically connect semiconductor components, then low parasitic capacitance is achieved, but additional space for looping and bonding is required and protective structures such as encapsulants are needed
Solution Approach 1:
The patent transitions from planar wire interconnects to three-dimensional stacked configurations with vertical vias. Through-holes penetrate the substrate vertically, allowing wires to connect bonding pads on opposite surfaces without requiring lateral looping space. This dimensional change eliminates the need for encapsulants while maintaining low parasitic capacitance.
Solution Approach 2:
The patent extracts and eliminates the encapsulant protective structure by using through-holes that pass completely through the substrate. The wires are directly exposed at both surfaces, removing the need for encapsulation while still providing mechanical support through the substrate itself.
2Ease of manufacture
If conventional interconnects are used for stacked semiconductor configurations, then manufacturing is simplified, but high-performance signal transmission with low parasitic capacitance and noise is not achieved
Solution Approach 1:
The patent segments the interconnect path into vertical via portions through the substrate and horizontal bonding portions on surfaces. This segmentation allows the substrate to act as a ground shield between stacked components, reducing noise and capacitance while maintaining manufacturing simplicity through conventional via formation techniques.
Solution Approach 2:
The substrate with through-holes serves as an intermediary structure that provides both mechanical support and electrical shielding. The grounded via walls act as a mediator to reduce electromagnetic interference and parasitic capacitance between stacked semiconductor components while using standard manufacturing processes.
3Reliability
If deposited conductors are used for interconnects, then high electrical conductivity is achieved, but low capacitance is not maintained
Solution Approach 1:
The patent applies different conductor configurations in different locations: deposited conductors are used where high conductivity is needed, while wire interconnects through vias are used where low capacitance is critical. The via walls provide localized shielding that reduces capacitance without compromising overall conductivity of the interconnect system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
TWIs enable efficient signal transmission with reduced capacitance and noise, allowing for the fabrication of high-density, high-performance stacked semiconductor components using conventional equipment and techniques.
Implementation Method 1
a bonded connection between the wire and the substrate contact
Implementation Method 2
a dielectric material in the via surrounding and electrically insulating the wire
Data Source
AI summary
A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.