Through Wire Interconnects for High-Density Semiconductor Stacking
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Solution Overview
Problem
Current semiconductor components face challenges with interconnects that either occupy excessive space, have low electrical conductivity, high capacitance, and reliability issues, or require expensive fabrication techniques, particularly in achieving high-density signal transmission with minimal parasitic capacitance and space usage.
Innovation Solution
The development of through wire interconnects that combine aspects of via and wire interconnects, using a conventional wire bonder to thread a wire through a via, form contacts on both sides of the substrate, and sever the wire to create a bonded contact, which provides electrical and thermal paths while accommodating thermal expansion and potentially filling the via with a material for structural support and insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If via interconnects are used to occupy space in the semiconductor substrate, then space utilization is improved, but electrical conductivity decreases and capacitance increases
Solution Approach 1:
The patent combines the space-filling advantage of via interconnects with the high conductivity advantage of wire interconnects by threading a wire through the via. This hybrid structure allows the via to occupy and define the interconnect location while the wire provides the actual conductive path, achieving both space utilization and high electrical conductivity simultaneously.
2Area of stationary object
If via interconnects are used for fabrication, then space utilization is improved, but manufacturing cost increases due to expensive equipment requirements
Solution Approach 1:
The wire acts as an intermediary element that bridges the via structure with conventional wire bonding equipment. Instead of requiring expensive via filling equipment, the patent uses the wire as a mediator that can be inserted through the via using standard wire bonding tools, thereby achieving via interconnect functionality with conventional manufacturing equipment.
3Reliability
If wire interconnects are used to achieve high conductivity, then electrical conductivity is improved, but space usage increases due to additional insulation requirements
Solution Approach 1:
The patent nests the wire interconnect within the via structure, with the wire positioned inside the via opening. This nested arrangement allows the wire to benefit from the via's precise location and structural support while minimizing the additional space required for insulation, as the via walls provide natural containment and spacing.
4Reliability
If wire interconnects are used for signal transmission, then capacitance is reduced, but reliability decreases due to temperature cycling issues
Solution Approach 1:
The patent applies different material properties to different parts of the interconnect structure: the wire provides low capacitance for signal transmission, while the via structure and bonding contacts provide thermal stability and mechanical strength. This local differentiation of material qualities allows each component to optimize its function while compensating for the weaknesses of the other under temperature cycling conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Through wire interconnects offer higher conductivity, lower capacitance, and improved reliability compared to conventional metal filled vias, enabling efficient signal transmission with reduced space usage and accommodating thermal expansion, while allowing for stacking of semiconductor components.
Implementation Method 1
The through wire interconnects are hybrids, which combine aspects of both via interconnects and wire interconnects... providing electrical and thermal paths
Implementation Method 2
The through wire interconnects are hybrids, which combine aspects of both via interconnects and wire interconnects... providing electrical and thermal paths
Implementation Method 3
improved reliability, particularly with temperature cycling... accommodating thermal expansion
Data Source
Figure 1A~1H
Figure 2A~2F
Figure 2G~2L
AI summary
A method for fabricating a semiconductor component (86) with a through wire interconnect (102) includes the step of providing a substrate (54) having a circuit side (62), a back side (64), and a through via (76). The method also includes the steps of: threading a wire (14) through the via (76), forming a contact (90) on the wire (14) on the back side (64), forming a bonded contact (92) on the wire (14) on the circuit side (62), and then severing the wire (14) from the bonded contact (92). The through wire interconnect includes (102) the wire (14) in the via (76), the contact (90) on the back side (64) and the bonded contact (92) on the circuit side (62). The contact (90) on the back side (64), and the bonded contact (92) on the circuit side (62), permit multiple components (86-1, 86-2, 86-3) to be stacked with electrical connections (170) between adjacent components. A system (120) for performing the method includes the substrate (54) with the via (76), and a wire bonder (10) having a bonding capillary (12) configured to thread the wire (14) through the via (76), and form the contact (90) and the bonded contact (92). The semiconductor component (86) can be used to form chip scale components, wafer scale components, stacked components (146), or interconnect components (861) for electrically engaging or testing other semiconductor components (156).