Through Wiring Area Insulation for Semiconductor Integration
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Solution Overview
Problem
The complexity of wiring structures in semiconductor devices, particularly in through wiring areas, poses challenges for efficient electrical connectivity between memory cell areas and peripheral circuits, leading to issues with integration and reliability.
Innovation Solution
The semiconductor device incorporates a through wiring area with a through contact plug surrounded by an insulating area, featuring vertical and horizontal extension portions of insulating layers, which electrically connects the memory cell area to the peripheral circuit area, enhancing integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a through contact plug is used to electrically connect memory cell area to peripheral circuit area, then electrical connectivity is improved, but wiring structure complexity increases
Solution Approach 1:
The insulating area is segmented into multiple insulating layers (first insulating layer, second insulating layer, third insulating layer) with different functions. Each layer is positioned at different heights and provides specific insulation functions, dividing the complex insulation task into manageable segments that simplify the overall wiring structure while maintaining reliable electrical connectivity.
Solution Approach 2:
The patent introduces a vertical dimension by stacking multiple insulating layers at different heights around the through contact plug. Instead of using a single complex lateral insulating structure, the solution extends into the vertical dimension, creating a multi-layered insulating area that simplifies the wiring structure while ensuring proper electrical isolation.
2Reliability
If multiple insulating layers are added to surround the through contact plug, then electrical isolation is improved, but manufacturing process complexity increases
Solution Approach 1:
The first insulating layer is formed preliminarily before the through contact plug is inserted, providing a pre-prepared insulating foundation. This preliminary action simplifies subsequent manufacturing steps by establishing the insulating structure in advance, reducing the complexity of the overall manufacturing process while ensuring proper electrical isolation.
Solution Approach 2:
The multiple insulating layers are nested around the through contact plug in a concentric manner, with each layer positioned at different heights. This nested structure efficiently provides comprehensive electrical isolation while using a compact arrangement that simplifies the manufacturing process compared to extended lateral insulation structures.
3Reliability
If the insulating area extends vertically and horizontally, then electrical connectivity stability is improved, but device area increases
Solution Approach 1:
The patent resolves the area conflict by extending the insulating area primarily in the vertical dimension through multiple stacked layers rather than expanding horizontally. The vertical extension portions provide stable electrical connectivity isolation without significantly increasing the horizontal device footprint, while horizontal extension portions are limited and strategically positioned.
Solution Approach 2:
The insulating area exhibits local quality variations with different extension characteristics in different regions. Vertical extension portions provide enhanced isolation where needed, while horizontal extension portions are localized to specific areas. This localized approach ensures stable electrical connectivity without unnecessarily increasing the overall device area.
Data Source
AI summary
A semiconductor device includes a peripheral circuit area disposed on a first substrate and including circuit devices. A memory cell area is disposed on a second substrate and includes memory cells. A through wiring area includes a through contact plug and an insulating area. The through contact plug extends through the memory cell area and the second substrate and connects the memory cell area to the circuit devices. The insulating area surrounds the through contact plug. The insulating area includes a first insulating layer penetrating through the second substrate, a plurality of second insulating layers, a third insulating layer having a vertical extension portion, and a plurality of horizontal extension portions extended in parallel to a top surface of the second substrate from a side surface of the vertical extension portion to contact the second insulating layers.