Data Throughput Estimation via CPU and Memory Curve Intersection

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Solution Overview

Problem

Existing software management solutions for modeling computer system throughput are too costly in terms of system resources, making it difficult to efficiently manage data throughput in a timely manner, especially in datacenters with multiple computer systems operating at different clock frequencies.

Innovation Solution

A method to dynamically estimate data throughput by modeling CPU subsystem throughput as a function of memory latency and memory subsystem latency as a function of bandwidth demanded, finding a point of intersection to represent the estimated operating point, allowing for efficient management of datacenter resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing software management solutions model computer system throughput, then system performance can be managed, but system resource overhead becomes too costly

Engineering Contradiction:
Improvethroughput modeling accuracyVSAvoidsystem resource overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transforms the complex throughput modeling problem into a simpler intersection-finding problem by changing the parameters from full system-state simulation to simple CPU throughput and memory latency curves. This allows accurate throughput estimation with minimal resource overhead by finding where the CPU throughput curve intersects with the memory latency curve.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extracts only the essential elements needed for throughput modeling (CPU throughput curve and memory latency curve) from the complex system, discarding unnecessary simulation details. This extraction enables lightweight modeling that requires minimal system resources while maintaining accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If throughput modeling is performed in real-time, then dynamic management is enabled, but computational cost increases

Engineering Contradiction:
Improvedynamic management speedVSAvoidcomputational energy
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent uses simple, computationally inexpensive curves (CPU throughput vs. memory latency) that can be rapidly calculated and discarded, replacing complex long-running simulations. These lightweight models enable frequent updates at low computational cost, supporting real-time dynamic management.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent pre-establishes the functional relationships between CPU throughput and memory latency, and between memory latency and bandwidth demand, so that real-time throughput estimation only requires finding curve intersections rather than performing complex simulations. This preliminary setup enables rapid responses to changing system conditions.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If multiple computer systems operate at different clock frequencies, then flexibility is improved, but workload distribution management becomes more difficult

Engineering Contradiction:
Improvefrequency flexibilityVSAvoidworkload distribution complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates a universal throughput estimation method based on CPU throughput curves and memory latency curves that works across computer systems with different clock frequencies. This universal approach eliminates the need for frequency-specific models, simplifying workload distribution management across heterogeneous systems.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9389919B2Managing workload distribution among computer systems based on intersection of throughput and latency models
Publication Date: 2016.07.12 HEWLETT PACKARD ENTERPRISE DEV LP
  • US9389919B2 patent drawing
  • US9389919B2 patent drawing
  • US9389919B2 patent drawing

AI summary

A method of determining an estimated data throughput capacity for a computer system includes the steps of creating a first model of data throughput of a central processing subsystem in the computer system as a function of latency of a memory subsystem of the computer system; creating a second model of the latency in the memory subsystem as a function of bandwidth demand of the memory subsystem; and finding a point of intersection of the first and second models. The point of intersection corresponds to a possible operating point for said computer system.