Thunder Array DRAM Underground Bitlines for Sub-5ns Cycle Times
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Solution Overview
Problem
Conventional DRAM structures face challenges in reducing refresh, write, and read cycle times due to high bitline and wordline capacitance and resistance, limiting their operational efficiency and compatibility with SRAM speeds.
Innovation Solution
The Thunder Array DRAM structure incorporates underground bitlines with reduced capacitance and resistance, utilizing large grain size Tungsten or Ruthenium for bitlines and wordlines, which decreases the RC time constant, enabling faster signal development and voltage rising/falling times, and eliminates serial-to-parallel and parallel-to-serial circuits for enhanced I/O data bus width flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DRAM structures are used with traditional bitline and wordline configurations, then manufacturing and design are straightforward, but the RC time constant is high resulting in slow signal development and long refresh/write/read cycle times
Solution Approach 1:
The patent moves the bitline from the traditional planar surface to an underground dimension, creating a three-dimensional structure where the bitline is positioned below the semiconductor substrate surface. This dimensional change reduces the capacitance between the bitline and surrounding structures, thereby reducing the RC time constant and improving signal development speed without significantly increasing overall device complexity
Solution Approach 2:
The patent employs large grain size Tungsten or Ruthenium materials for the bitline and wordline interconnections. These composite material choices provide superior electrical conductivity and lower resistance compared to conventional materials, directly reducing the RC time constant and enabling faster signal development while maintaining structural integrity
2Loss of time
If traditional bitline materials are used, then manufacturing processes are simple, but the resistance and capacitance are high leading to long cycle times
Solution Approach 1:
The patent changes the material parameters of the bitline by using large grain size Tungsten or Ruthenium instead of conventional materials. This parameter change reduces the resistance of the bitline, thereby reducing the RC time constant and shortening refresh and write cycle times. The large grain size structure is achieved through specific manufacturing processes that control crystal growth, balancing performance improvement with manufacturing feasibility
3Productivity
If conventional DRAM cell designs are used, then compatibility with existing processes is maintained, but operational speed is limited and SRAM compatibility is not achieved
Solution Approach 1:
The patent applies local quality improvement by enhancing specific components of the DRAM cell - particularly the bitline and wordline interconnections - while maintaining the standard 1T1C cell structure. The underground bitline configuration and large grain size materials provide locally optimized electrical characteristics that improve overall operational speed and SRAM compatibility without compromising the fundamental cell design or data retention reliability
Data Source
AI summary
A DRAM structure includes a semiconductor substrate, a plurality of DRAM cells, a Bitline, a sense amplifier, and a local wordline. The semiconductor substrate has a top surface. Each DRAM cell includes an access transistor and a storage capacitor. The Bitline has a first terminal extended along the plurality of DRAM cells to a second terminal, and the Bitline is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the Bitline. The local wordline is connected to a gate terminal of the access transistor of a first DRAM cell in the plurality of DRAM cells. A refresh cycle time, a write cycle time, or a read cycle time of the DRAM structure is less than 5 ns.