Light-Emitting Thyristor Chip for Compact Print Head Design
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Solution Overview
Problem
Conventional LED print heads face challenges in downsizing and cost reduction due to the complexity of wiring configurations, which affects the efficiency and size of electrophotographic image forming apparatuses.
Innovation Solution
The use of light-emitting thyristors with a pnpn structure and stacked semiconductor layers, along with a lower wiring configuration that reversely biases p-n junctions, allows for a reduced number of signal lines and a more compact design, enabling downsizing and cost-effective production of print heads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional wiring configurations are used in LED print heads, then electrical connectivity is achieved, but device complexity and print head width increase
Solution Approach 1:
The patent merges the lower wiring layer and upper wiring layer into a integrated stacked semiconductor structure. The lower wiring is formed in a lower semiconductor layer while the upper wiring is formed in an upper semiconductor layer, with both layers sharing common substrates and electrodes. This merging eliminates the need for separate wiring planes and reduces overall device complexity and width.
Solution Approach 2:
The patent transitions from planar wiring arrangements to a three-dimensional stacked configuration. By forming wirings in vertically stacked semiconductor layers rather than in a single plane, the design achieves better spatial utilization, reducing the horizontal width of the print head while maintaining all necessary electrical connections.
2Productivity
If conventional LED structures are used, then light emission is achieved, but the number of signal lines and overall size increase
Solution Approach 1:
The stacked semiconductor layers serve multiple functions simultaneously: they provide structural support, electrical connectivity through integrated wirings, and light emission through the LED structures. The lower and upper semiconductor layers are not just wiring carriers but also contain active light-emitting components, reducing the need for separate signal lines and control structures.
3Reliability
If complex wiring arrangements are implemented, then electrical connectivity is maintained, but manufacturing cost increases
Solution Approach 1:
The patent segments the wiring structure into distinct lower and upper semiconductor layers, each containing specific wiring elements. This segmentation allows for standardized fabrication processes for each layer, simplifying manufacturing compared to creating complex interwoven wiring patterns in a single layer. Each stacked layer can be fabricated using similar semiconductor processing techniques, reducing overall production cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the light-emitting chip's efficiency and reduces the width of the print head, facilitating downsizing and cost reduction while maintaining operational performance.
Implementation Method 1
having a semiconductor layer between the substrate and an uppermost semiconductor layer of the second stacked-semiconductor layer with the substrate than has a p-n junction between the substrate and the uppermost semiconductor layer of the second stacked-semiconductor layer reversely biased with respect to potentials respectively applied to the substrate and the uppermost semiconductor layer
Data Source
AI summary
The light-emitting chip includes: a substrate; plural light-emitting thyristors each having a pnpn structure formed of a first stacked-semiconductor layer in which at least 4 semiconductor layers having different conductivity types and including the substrate are stacked on the substrate; a lower wiring that is formed of a second stacked-semiconductor layer in which at least 3 semiconductor layers having different conductivity types and including the substrate are stacked on the substrate, and that has a semiconductor layer between the substrate and an uppermost semiconductor layer of the second stacked-semiconductor layer, the semiconductor layer having a fixed potential so that any one of p-n junctions between the substrate and the uppermost semiconductor layer is reversely biased with respect to potentials respectively applied to the substrate and the uppermost semiconductor layer; and an upper wiring provided on the lower wiring so as to intersect with the lower wiring through an isolation layer.