Multi-layer Thyristor DRAM Vertical Stacking and Epitaxy
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Solution Overview
Problem
Conventional DRAM technologies face challenges in scaling down memory cell area while maintaining capacitance and reducing leakage, with existing thyristor-based solutions experiencing performance degradation and process control issues due to epitaxial or CVD semiconductor layers and operation in the breakdown regime.
Innovation Solution
A multi-layer random access memory array structure is developed, featuring thyristor memory cells with vertical electrical connections and select transistors, using confined epitaxial lateral overgrowth of silicon to form pnpn regions, and incorporating assist gates to improve performance, along with shared bit lines and peripheral circuitry integrated on the same semiconductor substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional DRAM scaling is pursued to reduce cell area, then memory density increases, but capacitance maintenance and leakage reduction become significantly more difficult
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangements to a 3D vertical stack configuration. Multiple memory cell layers are stacked vertically with shared bit lines and select transistors, enabling increased storage density without proportionally increasing the footprint area. This vertical dimensionality change allows maintaining cell performance while achieving higher density.
2Ease of manufacture
If epitaxial or CVD semiconductor layers are used in thyristor-based DRAM, then manufacturing capability is improved, but device performance and yield degrade due to process complexity
Solution Approach 1:
The patent integrates the formation of pnpn thyristor regions directly into the CMOS fabrication process flow. Confined epitaxial lateral overgrowth is used to form thyristor structures in-situ during standard CMOS manufacturing, eliminating separate backend epitaxial or CVD processing steps. This merging of processes reduces thermal cycles and etch steps, thereby maintaining device performance and yield while achieving manufacturing capability.
3Adaptability or versatility
If thyristors are operated in forward and reverse breakdown region for data writing, then memory functionality is achieved, but process control and power consumption become challenging
Solution Approach 1:
The patent modifies the operating parameters of the thyristor by introducing an assist gate that can actively control the breakdown behavior. By applying appropriate voltages to the assist gate, the thyristor can be guided into controlled breakdown regions for data writing while maintaining better process control. This parameter control mechanism reduces uncontrolled power consumption during write operations while preserving memory functionality.
4Quantity of substance
If multi-layer vertical stacking is implemented to increase density, then bit density improves, but patterning complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the memory structure into multiple discrete layers separated by isolation dielectric material. Each layer contains memory cells with pnpn regions formed by confined epitaxial lateral overgrowth. This segmentation into manageable layers with clear isolation boundaries simplifies the patterning process for each individual layer while achieving high overall bit density through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances bit density, reduces patterning costs, and improves switching characteristics, standby stability, and power consumption of the memory array by enabling efficient vertical connections and selective addressing of memory cells, while maintaining low leakage and voltage operation.
Implementation Method 1
confined epitaxial lateral overgrowth of silicon to form pnpn regions
Data Source
AI summary
A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.