Adjustable-Trigger Thyristor ESD Clamp for Compact IC Protection
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Solution Overview
Problem
Integrated circuits are vulnerable to damage from electrostatic discharge (ESD) due to their susceptibility to over-limit electrical events, and existing ESD protection circuits often require a large footprint, which is undesirable for compact designs.
Innovation Solution
A compact ESD protection circuit is implemented using a conductive path circuit and a trigger circuit, where the trigger voltage is adjustable based on a control node's value, allowing for effective discharge of ESD currents through a thyristor or a combination of BJTs and PFETs, thereby protecting the circuitry without the need for large PFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large PFET is used to form an ESD clamp for protection, then the protection capability is improved, but the footprint area increases
Solution Approach 1:
The patent divides the ESD protection function into multiple smaller components: a first ESD protection circuit and a second ESD protection circuit, each handling different aspects of ESD protection. This segmentation allows the overall protection capability to be maintained while reducing the footprint of any single component, directly resolving the contradiction between protection capability and area occupation.
Solution Approach 2:
The patent combines multiple ESD protection circuits and operational amplifiers into an integrated operational transconductance amplifier (OTA) structure. By merging these functions into a unified circuit architecture, the patent achieves comprehensive ESD protection without requiring separate large-footprint components, thus maintaining reliability while reducing overall footprint.
2Reliability
If the trigger voltage is set low to protect circuitry before breakdown, then the protection threshold is improved, but the circuit may trigger during normal operation
Solution Approach 1:
The patent implements dynamic trigger voltage adjustment through operational amplifiers that respond to the operational state of the circuit. The trigger voltage is not fixed but adapts based on operating conditions, allowing the circuit to maintain a low protection threshold when needed while preventing false triggering during normal operation. This dynamic behavior resolves the contradiction between protection sensitivity and operational stability.
Solution Approach 2:
The patent employs feedback mechanisms through operational amplifiers that monitor circuit conditions and adjust the trigger voltage accordingly. This feedback ensures that the ESD protection circuit activates at the appropriate threshold while remaining stable during normal operation, effectively resolving the contradiction between low protection threshold and operational stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides effective protection against ESD events with a smaller footprint, ensuring the integrated circuitry is safeguarded from damage while maintaining operational integrity.
Implementation Method 1
The integrated circuitry often includes operational circuitry that includes circuit components, such as transistors, that are susceptible to damage caused by over-limit electrical events, for example, voltages caused by electrostatic discharge (ESD) during handling, testing and operation of the integrated circuit.
Implementation Method 2
Some dedicated ESD circuits include circuit components that exhibit a 'snap-back' characteristic. Generally, a snap-back characteristic provides a trigger condition which, when exceeded, causes the circuit to enter a low-impedance state.
Data Source
AI summary
Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.