Thyristor ESD Circuit Topology for Common Gate Oxide Processing

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Solution Overview

Problem

Existing semiconductor devices with electrostatic protection circuits face challenges in manufacturing efficiency due to the need for different gate film thicknesses for various transistors, particularly when high breakdown voltage CMOS is required, making it difficult to simplify the manufacturing process.

Innovation Solution

A circuit device incorporating a thyristor circuit, voltage hold circuit, trigger transistor, capacitor, and resistor configuration that allows for a common manufacturing process by eliminating the need for high breakdown voltage transistors, enabling wide voltage range operation and efficient electrostatic protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high breakdown voltage CMOS is used to achieve high voltage operation and electrostatic protection, then the breakdown voltage is improved, but the manufacturing process complexity increases due to different gate film thickness requirements

Engineering Contradiction:
Improvebreakdown voltageVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the circuit topology from using high breakdown voltage CMOS transistors to using a thyristor-based circuit with standard voltage transistors. This parameter change in the circuit architecture allows achieving high voltage protection functionality without requiring transistors with different gate film thicknesses, thus resolving the manufacturing process complexity while maintaining the breakdown voltage protection capability.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If different gate film thicknesses are used for various transistors to achieve high breakdown voltage, then the electrostatic protection capability is improved, but the manufacturing efficiency decreases

Engineering Contradiction:
Improveelectrostatic protection capabilityVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent employs a universal gate film thickness for all transistors in the circuit, making the manufacturing process universal and efficient. The thyristor circuit configuration enables electrostatic protection functionality to be achieved with standard voltage transistors, eliminating the need for specialized high breakdown voltage transistors with different gate film thicknesses, thus improving manufacturing efficiency while maintaining protection capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If high breakdown voltage transistors are used to ensure high voltage operation, then the voltage handling capability is improved, but the device complexity and cost increase

Engineering Contradiction:
Improvevoltage handling capabilityVSAvoidtransistor specification complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a thyristor circuit as an intermediary mechanism between the standard voltage transistors and the high voltage electrostatic discharge event. The thyristor circuit acts as a mediator that enables high voltage handling capability through its inherent thyristor structure, while the surrounding transistors can use standard gate film thickness, thus reducing device complexity and cost.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250210980A1Circuit Device
Publication Date: 2025.06.26 SEIKO EPSON CORP
  • US20250210980A1 patent drawing
  • US20250210980A1 patent drawing
  • US20250210980A1 patent drawing

AI summary

A circuit device 10 includes a first terminal T1, a second terminal T2, a thyristor circuit 20, a voltage hold circuit 30, a trigger transistor TT, a predetermined capacitor CS, and a predetermined resistor RS. The thyristor circuit 20 is provided between the first terminal T1 and a node NA that is a first node. The voltage hold circuit 30 is provided between the node NA, which is the first node, and the second terminal T2. The trigger transistor TT causes a trigger current to flow through the thyristor circuit 20. The predetermined capacitor CS is provided between the first terminal T1 and a gate of the trigger transistor TT. The predetermined resistor RS is provided between the gate of the trigger transistor TT and the second terminal T2.