Self-Aligned Thyristor Memory Fin Structures
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Solution Overview
Problem
Existing designs of thyristor random access memory (T-RAM) face challenges such as high manufacturing costs, non-self-aligned n-type and p-type bases, high operating voltage, short refresh time, and large cell size, which hinder efficient data storage and processing.
Innovation Solution
A thyristor-based memory device with a self-aligned structure integrated with CMOS processing, featuring a substrate with a well of one polarity type and regions of the opposite polarity type, along with a gate and heavily doped layers, which are self-aligned with the gate, enabling lower operating voltage, faster read/write operations, and a symmetrical two-bits-per-cell design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing T-RAM designs are used with non-self-aligned bases, then manufacturing processes are simpler, but manufacturing cost increases and precision decreases
Solution Approach 1:
The gate structure serves dual purposes: as the control electrode for the thyristor and as a self-aligned mask for forming the n-type and p-type base regions. The bases are formed adjacent to the gate sidewalls, automatically achieving precise alignment without requiring additional alignment steps or expensive SOI substrates
Solution Approach 2:
The gate structure is formed first before the base regions. This preliminary formation of the gate enables subsequent self-aligned ion implantation or epitaxial growth of the bases, ensuring precise positioning while simplifying the overall manufacturing process
2Quantity of substance
If conventional T-RAM structures are used, then cell size is larger, but storage density decreases
Solution Approach 1:
The invention transitions from planar device layout to three-dimensional fin structures. Multiple fins are formed in vertical arrays, allowing multiple memory cells to be stacked in the vertical dimension. Each fin can accommodate a complete thyristor structure, enabling high-density packing without increasing the lateral cell footprint
Solution Approach 2:
The memory device is divided into multiple independent fin structures, where each fin contains a complete thyristor. This segmentation allows parallel operation of multiple cells and enables scalable density improvement by simply adding more fins to the array
3Use of energy by moving object
If standard operating voltage is used, then device compatibility is better, but operating voltage consumption increases
Solution Approach 1:
The thyristor structure inherently provides high on-state current due to its regenerative feedback mechanism, enabling operation at reduced voltages. The device is designed to operate optimally at approximately 1.5V, which is lower than conventional DRAM voltages, while maintaining compatibility with standard CMOS fabrication processes through careful control of doping profiles and junction depths
4Speed
If fast read/write speed is achieved, then data access time decreases, but retention time shortens
Solution Approach 1:
The thyristor operates in its negative differential resistance region during read/write operations, enabling extremely fast switching speeds of approximately 1 nanosecond. The device dynamically transitions between high-current on-state and low-current off-state, providing both fast access and adequate retention (greater than 256 milliseconds) through controlled switching between operational modes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a compact, high-density memory device with improved performance in terms of lower operating voltage, faster read/write speeds, and longer retention times, while being compatible with existing logic technology and reducing manufacturing costs.
Implementation Method 1
Ion implantation is performed after silicide block formation
Implementation Method 2
This technology, which exploits the electrical property known as negative differential resistance and is called thin capacitively-coupled thyristor
Data Source
AI summary
Devices and methods for forming a device are presented. The device includes a substrate having a well of a first polarity type and a thyristor-based memory cell. The thyristor-based memory cell includes at least a first region of a second polarity type adjacent to the well, a gate which serves as a second word line disposed on the substrate, at least a first layer of the first polarity type disposed adjacent to the first region of the second polarity type and adjacent to the gate, and at least a heavily doped first layer of the second polarity type disposed on the first layer of the first polarity type and adjacent to the gate. At least the heavily doped first layer of the second polarity type is self-aligned with side of the gate.