Thyristor Memory Circuit Fin Structure Yield
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Solution Overview
Problem
The existing memory circuits with thyristors have low yield due to their stacked structure, making it difficult to integrate them into high-end semiconductor processes, and they face challenges in achieving high conduction current and low leakage current simultaneously.
Innovation Solution
The memory circuit incorporates a fin structure for at least one of the gates of the access transistor and the thyristor, formed on a silicon-on-insulator (SOI) structure layer, allowing for easier shrinkage and improved control efficiency, resulting in higher conduction current when active and lower leakage current when inactive.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a stacked structure is used for the memory circuit with thyristor, then conduction current is greater and writing speed is higher, but the yield is low and it is difficult to integrate into high-end semiconductor processes
Solution Approach 1:
The patent transitions from a planar two-dimensional structure to a three-dimensional FinFET structure with vertical fins. This dimensional change allows the gate to control the channel from multiple sides, improving control efficiency and enabling high-end semiconductor process integration while maintaining high conduction current through the vertical fin architecture.
Solution Approach 2:
The memory circuit is divided into multiple independent memory cells, each containing an access transistor and a thyristor. This segmentation allows for modular manufacturing and testing, improving overall yield by isolating defects to individual cells rather than affecting the entire circuit.
2Productivity
If a planar thyristor structure is used, then yield is improved, but the structure is difficult to shrink and cannot be imported into high-end semiconductor processes
Solution Approach 1:
The patent employs FinFET structures with vertical fins extending from the substrate, transforming the planar layout into a three-dimensional architecture. This enables continued scaling and shrinkability compatible with high-end semiconductor processes while maintaining manufacturing yield through improved gate control.
Solution Approach 2:
The gate structure wraps around the fin in a nested configuration, with the gate enclosing the channel region from multiple sides. This nested architecture provides superior electrostatic control and enables further miniaturization while maintaining device performance and yield.
3Ease of manufacture
If conventional planar transistors are used, then manufacturing is simpler, but conduction current is lower and leakage current is higher
Solution Approach 1:
The FinFET structure introduces vertical fins that increase the effective channel width without proportionally increasing the footprint. This three-dimensional approach enhances conduction current capability while the gate's multi-sided control improves switching efficiency, achieving better power characteristics with manageable manufacturing complexity.
4Ease of manufacture
If conventional planar transistors are used, then manufacturing is simpler, but leakage current is not sufficiently reduced
Solution Approach 1:
The vertical FinFET structure with its three-dimensional gate control provides superior electrostatic confinement of the channel, effectively suppressing leakage current. The gate's ability to control the channel from multiple sides creates stronger electric field confinement, reducing off-state leakage while maintaining manufacturing feasibility through standard semiconductor processes.
Data Source
AI summary
A memory circuit with thyristor includes a plurality of memory cells. Each memory cell of the plurality of memory cells includes an access transistor and a thyristor. The thyristor is coupled to the access transistor. At least one of a gate of the access transistor and a gate of the thyristor has a fin structure.