Cross-Coupled Thyristor SRAM Cell for Scalable Memory
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Solution Overview
Problem
CMOS SRAM devices face limitations in scalability and power consumption due to increasing statistical variations in MOS transistors as semiconductor processes shrink, making bipolar technology a more viable alternative for high-speed and low-power operation.
Innovation Solution
The development of a cross-coupled thyristor SRAM memory cell using bipolar transistors, which are adaptable for high-speed or low-power operation and can be integrated into existing CMOS technologies, allowing for the creation of tightly packed SRAM integrated circuits without the need for new fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If CMOS technology is used for SRAM devices, then manufacturing compatibility is maintained, but statistical variations increase and scalability is limited as processes shrink
Solution Approach 1:
The patent changes the fundamental device type from MOS transistors to bipolar transistors, altering the physical parameters of the memory cell. This parameter change enables better scalability and reduced statistical variations while maintaining compatibility with existing CMOS manufacturing processes through careful integration of bipolar devices into the established process flow.
2Productivity
If MOS transistors are scaled down for higher density, then circuit density increases, but statistical variations worsen
Solution Approach 1:
The patent transitions from MOS to bipolar transistor technology, fundamentally changing the device parameters. Bipolar transistors exhibit better scaling characteristics and lower statistical variations, allowing continued density improvement without the reliability degradation that plagues scaled MOS devices. This parameter change enables higher circuit density while maintaining or improving reliability.
3Speed
If bipolar technology is adopted for SRAM, then high-speed operation is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent merges bipolar transistor technology with existing CMOS manufacturing processes. By integrating bipolar devices into the established CMOS fabrication flow, the patent achieves high-speed bipolar operation while minimizing the increase in manufacturing complexity. The combined approach leverages the strengths of both technologies.
Solution Approach 2:
The patent creates a hybrid manufacturing process that can produce both bipolar and MOS devices using the same fabrication infrastructure. This universal approach allows the manufacturing facility to maintain existing CMOS capabilities while adding bipolar functionality, thereby achieving high-speed operation without proportionally increasing fabrication complexity.
Data Source
AI summary
A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.