TI-ADC Clock Divider Synchronization for Lower Metastability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Time-interleaved analog-to-digital converters (TI-ADCs) face challenges in achieving high sample rates while minimizing metastability errors, which can occur due to asynchronous control signals and the need for precise clock synchronization.
Innovation Solution
A multi-phase clock generator is designed with synchronized clock dividers, where the output clocks of each divider have a lower frequency than the input clocks, allowing more time for metastability to settle, thereby reducing the probability of metastability errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple ADC circuits are implemented in a time-interleaved manner to achieve high sample rates, then the overall sample rate increases, but metastability errors increase due to asynchronous control signals and clock synchronization issues
Solution Approach 1:
The patent divides the high-frequency clock signal into multiple lower-frequency clock signals using separate clock divider circuits for each ADC slice. This segmentation allows each slice to operate with a synchronized, lower-frequency clock, reducing metastability errors while maintaining the overall high sample rate through time-interleaved operation
Solution Approach 2:
The patent employs a feedback mechanism where the output of each clock divider is fed back to synchronize the operation of subsequent clock dividers. This feedback loop ensures that all clock signals remain synchronized, preventing metastability errors caused by asynchronous operation between slices
2Productivity
If clock dividers operate at high frequency to maintain high sample rate, then productivity is maintained, but metastability errors increase due to insufficient time for synchronization
Solution Approach 1:
The patent segments the clock division process into multiple stages, where each clock divider operates at a lower frequency than the input clock. This allows sufficient time for each stage to complete its division and synchronize before passing the clock signal to the next stage, reducing metastability errors while achieving the required overall sample rate
Solution Approach 2:
The patent performs preliminary clock division in multiple sequential stages before the final ADC conversion. Each stage prepares the clock signal at a lower frequency with adequate settling time, ensuring synchronization is established before the signal proceeds to the next processing stage
Data Source
AI summary
A TI-ADC circuit and method therefor include the use of first and second level clock generators configured to receive an asynchronous reference clock signal and generate a plurality of first and second clock signals, the second level clock generator including a plurality of clock dividers connected in series, respective ones of the plurality of clock dividers being configured to divide an input clock signal in accordance with a synchronization signal; a plurality of T/H circuits respectively configured to operate in accordance with one of the first clock signals; a plurality of sub-ADCs respectively configured to operate in accordance with one of the second clock signals, thereby to sample an input signal in a time-interleaved manner, wherein for a given clock divider of the plurality of clock dividers, the synchronization signal corresponds to an output clock of a clock divider immediately upstream from the given clock divider.