TI-ADC Frontend Buffering With Dynamic Common-Mode Adjustment
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (TI-ADCs) face performance degradation due to sensitivity to common-mode settings across Process, Voltage, and Temperature (PVT) variations, leading to increased bit-error rates and suboptimal data conversion, as the common-mode voltages of track-and-hold (T/H) and sub-ADC circuits are not easily optimized independently.
Innovation Solution
A common-mode adjusting circuit dynamically adjusts the input and output common-mode voltages of the source follower, positioned between the T/H and sub-ADC circuits, using digital-to-analog converters (DACs) and control loops to set optimal voltages based on PVT conditions, allowing independent control of T/H and sub-ADC common modes and compensating for DC offsets and baseline wandering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If common-mode voltages of T/H and sub-ADC circuits are set to fixed values, then circuit design is simplified, but performance degrades under PVT variations
Solution Approach 1:
The patent implements dynamic common-mode voltage adjustment by replacing fixed voltage sources with controllable voltage generators that can adapt their output levels in response to PVT variations. The common-mode control circuit continuously monitors process, voltage, and temperature changes and adjusts the common-mode voltages of T/H and sub-ADC circuits accordingly, transforming a static design into a dynamic adaptive system that maintains optimal performance across varying conditions.
Solution Approach 2:
The patent changes the common-mode voltage parameters of the T/H and sub-ADC circuits based on PVT conditions. By implementing voltage-controlled common-mode sources that can vary their output levels, the system optimizes the common-mode voltage parameters dynamically rather than using fixed values, thereby maintaining conversion accuracy and reducing bit-error rates under different process, voltage, and temperature scenarios.
2Measurement precision
If independent optimization of T/H and sub-ADC common modes is enabled, then conversion accuracy improves, but circuit complexity increases
Solution Approach 1:
The patent segments the common-mode control into separate independent control paths for the T/H circuit and the sub-ADC circuit. Each circuit has its own common-mode voltage generator and control mechanism, allowing independent optimization of their respective common-mode levels. This segmentation enables precise control of each circuit's common-mode voltage to maximize conversion accuracy while maintaining manageable circuit complexity through modular design.
Solution Approach 2:
The patent implements a universal common-mode control architecture that serves multiple functions: it independently controls T/H common-mode voltage, independently controls sub-ADC common-mode voltage, and adapts to PVT variations. The common-mode control circuit acts as a multi-functional block that can simultaneously perform different control tasks for different circuits, reducing overall system complexity while achieving independent optimization goals.
3Reliability
If common-mode settings are optimized for specific PVT conditions, then bit-error rate decreases, but adaptability to varying conditions is lost
Solution Approach 1:
The patent implements feedback mechanisms where the common-mode control circuit monitors actual PVT conditions and adjusts common-mode voltages in real-time. By continuously sensing process, voltage, and temperature variations and feeding this information back to the voltage generators, the system automatically optimizes common-mode settings to maintain low bit-error rates across varying conditions, transforming a static optimization into a dynamic adaptive process.
Solution Approach 2:
The common-mode control system performs self-adjustment based on monitored PVT conditions without requiring external intervention. The voltage-controlled common-mode sources automatically adapt their output levels in response to environmental changes, enabling the circuit to self-optimize its performance and maintain low bit-error rates across different operating conditions through autonomous adaptation.
Data Source
AI summary
A frontend circuit of a time-interleaved ADC is provided. The frontend circuit can include a track-and-hold circuit to sample an analog input signal to the ADC, a sub-ADC circuit to convert the sampled analog input signal to a digital output signal, and a source-follower circuit. An input of the source-follower circuit can be coupled to an output of the track-and-hold circuit, and an output of the source-follower circuit can be coupled to an input of the sub-ADC circuit. The source-follower circuit is to provide buffering between the track-and-hold circuit and the sub-ADC circuit. The circuit further includes a common-mode-adjusting circuit to dynamically adjust common-mode settings of the time-interleaved ADC. While adjusting the common-mode settings, the common-mode-adjusting circuit can adjust, separately, an input common-mode voltage of the track-and-hold circuit and an input common-mode voltage of the sub-ADC circuit based on current Process, Voltage, and Temperature (PVT) conditions.