Ti/Pt Electrode Structure for Lower Thermal Impedance in Laser Chips
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Solution Overview
Problem
High power semiconductor laser elements require high wall plug efficiency (WPE), but existing technologies have not effectively improved WPE due to limitations in electrode design and thermal impedance.
Innovation Solution
The electrode design includes a Ti layer and a Pt layer sequentially laid on a p-type semiconductor layer, with a thermal impedance per unit area of 1.2×10^4 K/W•m^2 or less, and specific film thicknesses for the Ti and Pt layers to maintain barrier metal functionality and reduce thermal resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the Ti layer thickness is reduced to lower thermal impedance, then thermal impedance decreases, but manufacturing precision becomes more difficult to control
Solution Approach 1:
The patent optimizes the Ti layer thickness to a specific range (5-35 nm) to achieve the desired thermal impedance while maintaining manufacturability. This parameter optimization resolves the contradiction by finding the optimal value that satisfies both thermal performance and manufacturing control requirements.
2Loss of energy
If the electrode layer thickness is reduced to lower thermal resistance, then thermal resistance decreases, but the barrier metal function may be compromised
Solution Approach 1:
The patent specifies optimal thickness ranges for both Ti (5-35 nm) and Pt (30-100 nm) layers to simultaneously achieve low thermal resistance and maintain effective barrier metal function. The Ti layer thickness is carefully controlled to prevent diffusion while the Pt layer provides sufficient barrier protection.
Solution Approach 2:
The patent uses a composite Ti/Pt layered structure where each material contributes different properties: Ti provides low thermal resistance and good adhesion, while Pt provides excellent barrier function. The combination of these materials in specific thickness ratios achieves both low thermal resistance and reliable barrier protection.
3Reliability
If thermal processing is performed to improve electrical contact, then electrical performance improves, but alloying between Ti and Pt layers occurs reducing thermal conductivity
Solution Approach 1:
The patent controls the thermal processing temperature range and duration to achieve adequate electrical contact without excessive alloying. By optimizing the processing parameters, the patent balances electrical performance improvement against thermal conductivity degradation from alloy formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the WPE of semiconductor laser elements by reducing thermal impedance and maintaining electrical performance, even with manufacturing deviations in the Ti layer.
Implementation Method 1
it is possible to maintain the function as a barrier metal of the Ti layer against the Pt layer on the upper layer side
Implementation Method 2
a thermal impedance per unit area of a contact portion that is in contact with the surface of the p-type semiconductor layer is equal to or smaller than 1.2×10^4 K/W•m^2
Implementation Method 3
the formation of TiPt3 due to alloying of the Ti layer and the Pt layer can be suppressed
Data Source
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AI summary
An object of the present invention is to improve the WPE of a semiconductor laser element. In an electrode including a Ti layer and a Pt layer that are sequentially laid on a surface of a p-type semiconductor layer, and the thermal impedance per unit area of a contact portion that is in contact with the surface of the p-type semiconductor layer is equal to or smaller than is equal to or smaller than 1.2×104(K/W•m2) The film thickness of the Ti layer is equal to or more than 5 nm and equal to or smaller than 35 nm. The sum of the film thickness of the Ti layer and the film thickness of the Pt layer is equal to or smaller than 70 nm. The film thickness of the Pt layer is equal to or more than 0.7 times and equal to or smaller than 1 time the film thickness of the Ti layer. An Au layer is further laid on the Pt layer. A chip-on-mount is fabricated by fixing a semiconductor laser element, in which the electrode is provided on the p-type semiconductor layer, on a mount in a junction-down configuration.