Transimpedance Amplifier AGC Circuit for Fast Burst-Mode Settling
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Solution Overview
Problem
Traditional automatic gain control circuits for transimpedance amplifiers in burst-mode GPON systems face challenges in achieving fast response times due to the requirement for low cutoff frequencies, which conflicts with the need to minimize jitter and pulse-width distortion, especially in systems using NRZ coding with stringent time series requirements.
Innovation Solution
The proposed automatic gain control circuit employs identical NMOS transistors with a common turn-on voltage threshold and a bias current source to form negative feedback loops, allowing the transimpedance amplifier to adjust its output voltage without needing a low turn-on voltage threshold, enabling fast response and minimizing distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a low cutoff frequency is used in the AGC feedback loop to minimize jitter and pulse-width distortion, then signal quality is improved, but the AGC loop settling time increases to dozens of microseconds, making it unsuitable for burst-mode operation
Solution Approach 1:
The patent segments the feedback loop into two independent paths: a slow AGC loop for gain control and a fast local feedback loop for immediate distortion correction. This segmentation allows each loop to operate at its optimal speed without compromising the other, resolving the contradiction between signal quality and settling time.
Solution Approach 2:
The patent introduces an intermediary circuit that detects output signal distortion and generates a fast correction signal. This intermediary acts as a mediator between the slow AGC loop and the output, providing immediate correction for pulse-width distortion without requiring the entire AGC loop to settle quickly.
2Reliability
If the AGC loop cutoff frequency is lowered to ensure acceptable jitter performance, then jitter is reduced, but the loop requires longer settling time of dozens of microseconds
Solution Approach 1:
The feedback system is divided into two segments: the main AGC loop operating at low cutoff frequency for jitter control, and a separate fast local feedback loop for rapid settling. This segmentation enables the system to maintain low jitter while achieving fast response in burst-mode operation.
Solution Approach 2:
The fast local feedback loop performs preliminary correction of output distortion before the main AGC loop completes its settling process. This preliminary action ensures that jitter performance is maintained while the overall system settles quickly enough for burst-mode operation.
3Speed
If traditional AGC method is used with low cutoff frequency below 5 MHz to stabilize within 36 ns preamble time, then burst-mode response time is improved, but DC wandering increases and jitter is not minimized
Solution Approach 1:
The patent segments the feedback functions into two independent loops: the main AGC loop operates at low cutoff frequency to minimize jitter and DC wandering, while the fast local feedback loop provides rapid response for burst-mode operation. This segmentation resolves the contradiction between speed and stability.
Solution Approach 2:
The fast local feedback loop acts as an intermediary that provides immediate correction for burst-mode response without compromising the low cutoff frequency setting of the main AGC loop. This intermediary enables fast response while maintaining jitter and DC stability.
Data Source
AI summary
An automatic gain control circuit of a transimpedance amplifier includes a transimpedance amplifier TIA1, a transimpedance amplifier TIA2, an NMOS transistor Q1, an NMOS transistor Q2, an error amplifier U3, and a bias current source Ib. An input terminal and an output terminal of the transimpedance amplifier TIA1 are connected to a drain and a source of the NMOS transistor Q1, respectively. An input terminal and an output terminal of the transimpedance amplifier TIA2 are connected to a drain and a source of the NMOS transistor Q2, respectively. An output terminal of the bias current source Ib is connected to a positive input terminal of the error amplifier U3 and the drain of the MOS transistor Q2.