TIA Output DC Level Boosting With Stable DC-Restore Loop
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Solution Overview
Problem
Conventional transimpedance amplifiers face challenges in matching the output DC level of the transimpedance amplification stage with the input DC level of the differential amplification stage, leading to instability due to variations in input current and production deviations, which affects the overall circuit stability.
Innovation Solution
A circuit comprising a transimpedance amplification stage, a differential amplification stage, a level boosting unit, and a DC-restore loop, where the level boosting unit includes a tail current source and a capacitor, and the DC-restore loop features a pseudo transimpedance amplification stage, operational amplifier, and filter units to maintain DC level matching and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If a CS amplification stage is added to boost the output DC level of the transimpedance amplification stage, then the DC level matching between stages is improved, but the circuit complexity increases and the stability deteriorates due to bias current variations
Solution Approach 1:
The patent merges the level boosting function into the existing transimpedance amplification stage by adding a tail current source to the NMOS transistor, rather than adding a separate CS amplification stage. This integration achieves DC level boosting while avoiding the additional complexity and stability issues that would arise from adding another independent amplification stage.
Solution Approach 2:
The tail current source added to the NMOS transistor serves multiple functions: it provides the necessary DC level boosting while also maintaining bias stability against input current variations. This multi-functional approach eliminates the need for separate biasing circuits and reduces overall circuit complexity while improving stability.
2Device complexity
If the bias current of the CS amplification stage is determined by the transimpedance amplification stage, then the circuit simplicity is maintained, but the stability deteriorates when input current varies or production deviations occur
Solution Approach 1:
The patent implements a feedback mechanism where the output of the operational amplifier connects back to the gate of the NMOS transistor in the transimpedance amplification stage. This feedback loop automatically adjusts the gate voltage to maintain stable bias current despite variations in input current or production deviations, thereby improving circuit reliability without adding significant complexity.
Solution Approach 2:
The patent uses the operational amplifier to maintain equal potential conditions at its input terminals, ensuring that the DC level at the output of the transimpedance amplification stage matches the required input DC level of the differential amplification stage. This equipotential approach ensures stable operation across varying conditions.
3Shape
If a tail current source is added to the transimpedance amplification stage to boost output DC level, then the DC level matching is improved without additional intermediate stages, but the circuit complexity increases
Solution Approach 1:
The patent merges the level boosting function into the existing transimpedance amplification stage by adding a tail current source to the NMOS transistor, rather than adding a separate CS amplification stage. This integration achieves DC level boosting while avoiding the additional complexity and stability issues that would arise from adding another independent amplification stage.
Data Source
AI summary
A circuit for increasing an output direct-current level of a transimpedance amplification stage in a TIA (Trans-Impedance Amplifier) includes a transimpedance amplification stage, a differential amplification stage, a level boosting unit, and a DC-restore loop. An input terminal of the transimpedance amplification stage is used for inputting a photocurrent signal. An output terminal of the transimpedance amplification stage is directly connected to an input terminal of the differential amplification stage.