Transimpedance Amplifier MOS Load for High-Speed Gain Headroom
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Solution Overview
Problem
Transimpedance amplifiers face a constraint on gain due to limited voltage headroom when attempting to increase speed, as higher bias currents require smaller load resistor values, limiting their high-speed performance.
Innovation Solution
Incorporating a diode-connected MOS load circuit with a resistor coupling the gate and drain terminals of PMOS transistors, and optionally using a current mirror with adjustable gain through NMOS transistors, to increase speed without significant gain sacrifice.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bias current is increased to increase the speed of TIA, then the speed is improved, but the voltage headroom is reduced which limits the gain
Solution Approach 1:
The patent changes the load circuit configuration from a simple resistor to a diode-connected MOS transistor with a resistor between gate and drain. This parameter change allows the load to provide higher output resistance (higher gain) while consuming less voltage headroom, enabling both high speed and high gain to be achieved simultaneously. The diode-connected MOS structure fundamentally alters the voltage-current relationship in the load circuit.
2Speed
If the resistance value of the load resistor is decreased to allow higher bias current, then the speed is improved, but the gain is reduced
Solution Approach 1:
The patent transforms the load resistor into a diode-connected MOS transistor configuration. This changes the effective resistance characteristics - the MOS transistor in diode connection provides a non-linear resistance that can be optimized to provide both fast response (for high speed) and high output resistance (for high gain). The resistor between gate and drain further fine-tunes this resistance parameter.
Solution Approach 2:
The diode-connected MOS transistor introduces dynamic behavior to the load circuit. The effective resistance of the MOS transistor changes with operating conditions, allowing the circuit to optimize between speed and gain based on the signal characteristics and bias conditions, rather than being constrained by a fixed resistor value.
3Device complexity
If the voltage headroom is constrained by the voltage difference between VDD and VSS, then the circuit is simplified, but the gain is limited
Solution Approach 1:
The patent changes the load element from a linear resistor to a diode-connected MOS transistor, which fundamentally alters how voltage headroom is utilized. The MOS transistor configuration provides higher effective resistance and better voltage utilization efficiency, extracting more gain per volt of headroom available. This parameter change allows high gain to be achieved without proportionally increasing the voltage headroom requirement.
Data Source
AI summary
A transimpedance method and apparatus are provided. In one implementation an apparatus includes a common-gate amplifier for receiving a first current from a first circuit node and outputting a second current to a second circuit node, and a load circuit coupled to the second circuit node, the load circuit comprising a diode-connected MOS (metal-oxide semiconductor field effect transistor), wherein a gate terminal of the MOS is coupled to a drain terminal of the MOS via a resistor. In one embodiment, a current-mode input is injected to the first circuit node and the apparatus further comprises a biasing circuit for outputting a substantially constant current to the first circuit node.