TIADC Sampling Clock Phase Error Estimation Across Frequency Bands
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Solution Overview
Problem
The estimation error of sampling clock phase mismatch error in time-interleaved analog to digital converters (TIADCs) increases with the number of sub-ADCs, affecting the performance of 5G mobile communication systems, particularly due to the difficulty in achieving symmetry and matching among multiple channels.
Innovation Solution
A method and apparatus that divide the proportional relation of the modular square subtraction method into frequency intervals, perform offline statistics on slope and offset values, and use interpolation to estimate the actual sampling clock phase mismatch error in real-time, improving estimation precision without excessive complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If the modular square subtraction method is used for sampling clock phase mismatch error estimation, then the estimation can be performed in all-digital blind self-adaptive manner, but the estimation error increases as the number of sub-ADCs increases
Solution Approach 1:
The frequency range is divided into multiple frequency intervals, with each interval having its own proportional relation model. This segmentation allows the system to maintain higher estimation precision across different frequency ranges while preserving the automated estimation capability through interval-based modeling.
Solution Approach 2:
The proportional relation parameters (slope and offset) are changed according to different frequency intervals. By adapting these parameters to specific frequency ranges through offline statistics and online interpolation, the system maintains accurate error estimation despite varying numbers of sub-ADCs.
2Speed
If multiple sub-ADCs are used to improve sampling rate exponentially, then the sampling rate increases, but symmetry and matching among multiple channels become difficult to achieve
Solution Approach 1:
The system performs self-diagnosis and self-correction by automatically estimating sampling clock phase mismatch errors through the modular square subtraction method. This self-service approach compensates for manufacturing imperfections without requiring external calibration equipment or manual adjustment.
Solution Approach 2:
The error estimation results are fed back to compensate for phase mismatch errors in real-time. This feedback mechanism continuously corrects channel asymmetry and matching issues, allowing the system to maintain high sampling rates despite manufacturing variations.
3Device complexity
If sampling clock phase mismatch errors are not compensated, then the system design is simpler, but the performance of the whole system is seriously affected
Solution Approach 1:
The patent replaces complex hardware-based error compensation mechanisms with an all-digital signal processing approach. By using digital modular square subtraction and proportional relation modeling, the system achieves error compensation without additional analog components or complex hardware modifications.
Data Source
AI summary
Provided are a sampling clock phase mismatch error estimation method and apparatus, and a storage medium. This sampling clock phase mismatch error estimation method includes: a proportional relation between an estimation operator of a modular square subtraction method corresponding to each frequency interval of multiple frequency intervals and a sampling clock phase mismatch error of a time-interleaved analog to digital converter (TIADC) is acquired; a slope and an offset value of a fitting proportion line segment are counted; and a slope of a proportion line segment corresponding to a real-time estimation frequency is converted, and an offset value corresponding to the real-time estimation frequency is estimated through an interpolation according to a counted slope and a counted offset value, and the actual value of the sampling clock phase mismatch error is estimated according to a converted slope and an offset value estimated through the interpolation.