Asynchronous TIADC Code Correction for Timing Skew Tone Suppression

Solution Overview

Problem

Time-interleaved analog-to-digital converters (TIADCs) face issues with timing skew tone due to sampling timing skew, which is typically addressed by adding an additional sub-ADC, increasing circuit area and cost.

Innovation Solution

A TIADC configuration with asynchronous sub-ADCs, a control circuit, a sub-ADC selection circuit, and a digital code correction and selection circuit, which selects and corrects digital output codes to suppress timing skew tone without requiring additional sub-ADCs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If an additional sub-ADC is added to suppress timing skew tone, then the timing skew tone is suppressed, but the circuit area and cost increase

Engineering Contradiction:

Improvetiming skew toneVSAvoidcircuit area

Core Design Contradiction:

Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The patent extracts and removes the harmful timing skew tone through a cancellation mechanism that identifies and subtracts the skew tone component from the digital output codes, rather than adding more sub-ADCs to suppress it

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a skew tone cancellation circuit as an intermediary component that processes the digital output codes to eliminate timing skew tone, serving as a mediator between the sub-ADCs and the final output

Inventive Principle:

Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If an additional sub-ADC is added to suppress timing skew tone, then the timing skew tone is suppressed, but the cost increases

Engineering Contradiction:

Improvetiming skew toneVSAvoidcost

Core Design Contradiction:

Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The patent extracts and removes the harmful timing skew tone through a cancellation mechanism that identifies and subtracts the skew tone component from the digital output codes, rather than adding more sub-ADCs to suppress it

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a skew tone cancellation circuit as an intermediary component that processes the digital output codes to eliminate timing skew tone, serving as a mediator between the sub-ADCs and the final output

Inventive Principle:

Principle #24Intermediary (Mediator)

3Area of stationary object

If asynchronous sub-ADCs are used with random selection, then circuit area is reduced, but timing skew tone must be suppressed through correction

Engineering Contradiction:

Improvecircuit areaVSAvoiddigital code correction complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent extracts and removes the harmful timing skew tone through a cancellation mechanism that identifies and subtracts the skew tone component from the digital output codes

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a skew tone cancellation circuit as an intermediary component that processes the digital output codes to eliminate timing skew tone

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250226836A1Time-interleaved analog-to-digital converter and operation method thereof

Publication Date: 2025.07.10 REALTEK SEMICON CORP

AI summary

A method of operating a time-interleaved analog-to-digital converter (TIADC). The TIADC converts an input signal to generate a digital output signal and includes multiple asynchronous sub-ADCs. The asynchronous sub-ADCs each convert the input signal at a different time point to generate a digital output code, and each of the asynchronous sub-ADCs generates a completion signal upon completion of an analog-to-digital conversion operation. The method includes the following steps: generating an indication signal according to the completion signals, wherein the indication signal indicates multiple candidate sub-ADCs; selecting one of the candidate sub-ADCs as a target sub-ADC according to the indication signal; and correcting the digital output code of the target sub-ADC to generate the digital output signal.