TIADC Reference Sampling for Timing Skew Tone Suppression
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Solution Overview
Problem
Conventional time-interleaved analog-to-digital converters (TIADCs) face challenges in suppressing residual timing skew tones due to phase errors among sub-ADCs, leading to performance degradation and errors in other circuits, with existing correction methods being slow in convergence and leaving residual tones.
Innovation Solution
A TIADC system that includes multiple ADCs, a reference ADC, a digital correction circuit, and a control circuit, operating in two modes: the first mode corrects digital output codes using a reference signal to eliminate timing skew, gain, and offset tones, while the second mode randomly outputs corrected codes and the reference code to further suppress these tones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional correction methods using three filters are used to adjust digital output codes according to phase error values, then phase errors can be compensated, but the convergence is slow and residual timing skew tones remain
Solution Approach 1:
The patent makes the sampling clocks dynamic by introducing random phase shifts to the sampling clocks of sub-ADCs. This dynamic adjustment allows the system to break the fixed periodic pattern that causes residual timing skew tones, enabling faster convergence and more effective suppression of timing skew tones while maintaining phase error compensation capability.
2Measurement precision
If conventional correction methods are used to compensate phase errors, then some correction is achieved, but residual timing skew tones, gain tones, and offset tones remain which degrade performance
Solution Approach 1:
The patent introduces random phase shifts to the sampling clocks of sub-ADCs, making the sampling timing dynamic rather than fixed. This dynamic adjustment disrupts the periodic pattern that generates residual timing skew tones, effectively suppressing these harmful factors while maintaining the phase error compensation function.
Solution Approach 2:
The patent changes the phase parameter of sampling clocks by introducing random phase shifts. This parameter change transforms the fixed phase relationships into variable ones, preventing the generation of residual timing skew tones and improving overall system performance by eliminating harmful spectral components.
Data Source
AI summary
A time-interleaved analog-to-digital converter (TIADC) operates in a first mode or a second mode and includes M analog-to-digital converters (ADCs), a reference ADC, a digital correction circuit, and a control circuit. The M ADCs sample an input signal according to M enable signals to generate M digital output codes. The reference ADC samples the input signal according to a reference enable signal to generate a reference digital output code. The digital correction circuit corrects the M digital output codes to generate M corrected digital output codes. The control circuit generates the M enable signals and the reference enable signal according to a clock. The control circuit outputs the M corrected digital output codes in turn but does not output the reference digital output code in the first mode and randomly outputs the M corrected digital output codes and the reference digital output code in the second mode.