Tie-high and tie-low circuits with active resistor decoupling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing tie-high and tie-low circuits used for protecting standard cell inputs from electrostatic discharge (ESD) are complex and large in size due to their structure, which combines pull-up/down PMOS/NMOS transistors with additional circuits, making them inefficient for decoupling capacitance.
Innovation Solution
A simplified structure for tie-high and tie-low circuits is introduced, where a PMOS transistor is connected to a power rail and an NMOS transistor is connected to a ground rail, with a decoupling capacitor, and either the source or drain of the NMOS/PMOS transistor is connected to the gate via an active resistor, allowing for effective voltage division and increased decoupling capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complex structure combining pull-up/down PMOS/NMOS transistors with additional circuits is used for tie-high/tie-low cells, then the ESD protection function is achieved, but the device complexity and size increase
Solution Approach 1:
The patent extracts the essential function of tie-high/tie-low cells (maintaining fixed voltage levels and providing ESD protection) by using a single PMOS or NMOS transistor with an active resistor, removing the complex additional circuits while preserving the core protection function
Solution Approach 2:
The simplified transistor structure with active resistor serves multiple functions simultaneously: it provides ESD protection, maintains fixed voltage levels, and increases decoupling capacitance, replacing the need for separate complex circuits
2Reliability
If a complex structure combining pull-up/down PMOS/NMOS transistors with additional circuits is used for tie-high/tie-low cells, then the ESD protection function is achieved, but the area occupied increases
Solution Approach 1:
The patent removes unnecessary additional circuits from the conventional structure, retaining only the essential transistor and active resistor components, thereby significantly reducing the cell area while maintaining ESD protection capability
Solution Approach 2:
The patent combines the ESD protection function and decoupling capacitance function into a single transistor-active resistor structure, reducing the total area required compared to separate implementations
3Reliability
If conventional tie-high/tie-low cells are used, then the structure is well-established, but the decoupling capacitance is insufficient
Solution Approach 1:
The patent changes the electrical parameters of the cell by introducing an active resistor with specific resistance characteristics, which transforms the transistor into a structure that provides both voltage stability and increased decoupling capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution simplifies the structure and increases decoupling capacitance, effectively protecting against ESD and enhancing noise reduction in the supply node by dividing the supply voltage according to the resistance ratio of the transistors, resulting in a more efficient and compact design.
Implementation Method 1
a decoupling capacitor connected to a ground rail in the standard cell library and the PMOS transistor
Implementation Method 2
either one of the source and the drain of the NMOS transistor being connected to the ground rail via an active resistor
Data Source
AI summary
A tie-high circuit includes: a p-type metal-oxide-semiconductor (PMOS) transistor connected to a power rail in a standard cell library; and a decoupling capacitor connected to a ground rail in the standard cell library and the PMOS transistor. The decoupling capacitor includes an n-type metal-oxide-semiconductor (NMOS) transistor having either one of a source and a drain of the NMOS transistor being connected to the ground rail via an active resistor. A tie-low circuit includes: an n-type metal-oxide-semiconductor (NMOS) transistor connected to a ground rail in a standard cell library; and a decoupling capacitor connected to a power rail in the standard cell library and the NMOS transistor. The decoupling capacitor of the tie-low circuit includes a PMOS transistor having either one of a source and a drain of the PMOS transistor being connected to the power rail via an active resistor.