Tie-Off Transistor Layout for FinFET Isolation in Tight IC Area
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Solution Overview
Problem
As integrated circuit devices become smaller, electromagnetic interference among adjacent devices such as FinFETs becomes a challenge, and existing isolation methods are inefficient in terms of device area usage and electrical isolation.
Innovation Solution
The use of a poly gate positioned at the threshold voltage boundary of multi-threshold voltage IC devices, connected directly to a power rail via a conductive via, to maintain the tie-off transistor in an off state, thereby electrically isolating adjacent transistors and optimizing device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional isolation methods are used between adjacent FinFET devices, then electrical isolation is achieved, but device area efficiency deteriorates and electromagnetic interference is not sufficiently reduced
Solution Approach 1:
The tie-off device merges multiple functions into a single structure: it provides electrical isolation between adjacent FinFETs, consumes minimal area by utilizing the threshold voltage boundary region, and reduces electromagnetic interference through its off-state configuration. The gate of the tie-off device is connected to a power rail to maintain it in a permanent off state, effectively combining isolation, space optimization, and EMI reduction in one element.
2Productivity
If device spacing is reduced to increase integration density, then productivity improves, but electromagnetic interference among adjacent devices worsens
Solution Approach 1:
The tie-off device acts as an intermediary element positioned at the threshold voltage boundary between adjacent FinFETs. It provides electrical isolation and EMI shielding while occupying minimal space, enabling higher integration density without suffering from electromagnetic interference. The intermediary structure allows devices to be placed closer together while maintaining electrical separation.
3Reliability
If tie-off device gate is connected to power rail, then electrical isolation reliability improves, but device complexity increases
Solution Approach 1:
The tie-off device is configured to automatically maintain its off state through a direct connection between its gate and the power rail. This self-service configuration eliminates the need for additional control circuitry or complex biasing networks, achieving reliable isolation with minimal structural complexity. The device serves itself by using the power rail connection to establish and maintain the required gate voltage.
Data Source
AI summary
An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.