Semiconductor Tier Decoupling Structure for Alignment and Low Capacitance

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Solution Overview

Problem

Challenges arise during the scaling-down process of semiconductor devices in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in optical recognition and parasitic capacitance.

Innovation Solution

A semiconductor device design featuring a first and second tier structure with decoupling units and alignment marks made of low-k dielectric material and fluorescent material, which includes a bottle-shaped cross-sectional profile to improve optical recognition and reduce parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional alignment marks are used during wafer fabrication, then manufacturing process is simple, but optical recognition is insufficient leading to reduced yield

Engineering Contradiction:
Improveoptical recognitionVSAvoidyield
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent applies fluorescent materials to alignment marks that change their optical properties under specific excitation wavelengths. The fluorescent alignment marks emit light at different wavelengths than the excitation source, enabling enhanced optical recognition and differentiation from surrounding structures during wafer fabrication, thereby improving measurement precision and yield

Inventive Principle:
Principle #32Color changes

Solution Approach 2:

The patent introduces fluorescent materials as intermediary substances between the alignment mark structure and the optical detection system. These fluorescent materials act as mediators that convert incident light into detectable fluorescent signals, enhancing the optical contrast and recognition capability without modifying the underlying alignment mark geometry

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If conventional dielectric materials are used in decoupling units, then manufacturing is straightforward, but parasitic capacitance is high affecting device performance

Engineering Contradiction:
Improvedevice performanceVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the dielectric constant parameter of the decoupling unit material by using low-k dielectric materials with dielectric constants significantly lower than conventional materials. This parameter change reduces the parasitic capacitance formed between adjacent conductive features, thereby improving device performance and reliability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite low-k dielectric materials that combine organic and inorganic components to achieve both low dielectric constant and mechanical reliability. These composite materials provide optimized electrical properties for reducing parasitic capacitance while maintaining structural integrity and manufacturability

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design enhances optical recognition during wafer fabrication, improving yield and reducing parasitic capacitance of conductive features.

Implementation Method 1

a first set of solid alignment marks including a first-tier-alignment mark positioned on the decoupling unit of the first tier structure, and including a fluorescent material

Methodology Applied
Scientific EffectFluorescence: Fluorescence

Data Source

PatentUS12381157B2Semiconductor device with an insulative decoupling unit positioned between two of a plurality of conductive features
Publication Date: 2025.08.05 NAN YA TECH
  • US12381157B2 patent drawing
  • US12381157B2 patent drawing
  • US12381157B2 patent drawing

AI summary

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first tier structure positioned on a substrate and including: a plurality of conductive features of the first tier structure positioned over the substrate, and a decoupling unit of the first tier structure positioned between the plurality of conductive features of the first tier structure, and including a bottle-shaped cross-sectional profile; a first set of solid alignment marks including: a first-tier-alignment mark of the first set of solid alignment marks positioned on the decoupling unit of the first tier structure; a first set of spaced alignment marks including: a first-tier-alignment mark of the first set of spaced alignment marks positioned in a mirror manner of the first-tier-alignment mark of the first set of solid alignment marks according to a first axis of symmetry.