Tier Recess Liner Sequencing for Vertical NAND Etch Depth Control
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Solution Overview
Problem
The increasing aspect ratios of openings and number of layers in vertical memory arrays make it difficult to control the selective nitride etch process, leading to varying etch depths and potential defects in dielectric structures, which can cause failures in subsequent processing steps.
Innovation Solution
The use of multiple etch stop liners in tapered openings allows for precise control of nitride etch depths, forming cantilevered dielectric arms of varying lengths to maintain structural integrity and prevent damage during replacement with conductive materials, enhancing the reliability of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the aspect ratio of openings and number of layers are increased to improve memory density, then memory capacity is improved, but control of the selective nitride etch process becomes increasingly difficult
Solution Approach 1:
The patent divides the single etch process into multiple sequential etch processes, each targeting specific depth ranges. The first etch process removes nitride layers at shallower depths, the second etch process removes nitride layers at greater depths, and subsequent etch processes continue this pattern. This segmentation allows precise control over etch depths even in high aspect ratio openings with many layers, resolving the contradiction between increased memory density and maintained etch control precision.
2Ease of manufacture
If a single etch process is used to remove nitride layers, then the process is simpler, but varying etch depths cause defects in dielectric structures
Solution Approach 1:
The patent segments the etch process into multiple controlled steps with different depth targets. Each etch process is designed to remove nitride layers within a specific depth range while preserving dielectric structures at other depths. This multi-step approach eliminates the defects caused by varying etch depths that would result from a single etch process, while maintaining manufacturing feasibility through systematic process design.
Solution Approach 2:
The patent applies preliminary protective measures by forming etch stop liners at specific depths before conducting etch processes. These liners are strategically placed to protect dielectric structures from over-etching. By preparing these protective structures in advance, the patent ensures dielectric integrity is maintained throughout the multi-step etch process, preventing defects before they occur.
3Adaptability or versatility
If nitride layers are selectively removed to form control gates, then device functionality is achieved, but dielectric structures may be damaged in subsequent processing steps
Solution Approach 1:
The patent forms etch stop liners at predetermined depths within the dielectric stack before conducting the selective nitride removal process. These liners act as protective barriers that prevent etch damage to dielectric structures during and after the nitride removal process. By preparing these protective structures in advance, the patent ensures dielectric structures remain resilient and undamaged while still achieving the required device functionality through selective nitride layer removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more uniform and resilient dielectric structures, reducing failure rates and improving the quality and reliability of semiconductor devices, particularly in vertically stacked NAND memory arrays, while also reducing production costs.
Implementation Method 1
A second etch process selectively etches away at least a portion of the layers of the nitride materials in regions of the tier stack adjacent to walls of the tapered opening, and leaves intact the dielectric layers
Data Source
AI summary
A method for making a vertical contact through levels of a memory device. A first liner is formed in an opening, and a second liner is formed over the first liner. The first liner is selectively removed from under the second liner to expose a first portion of the opening, such that the first liner remains intact over a second portion of the opening. The second liner is then removed, leaving the first liner overlying the second portion of the opening. A first portion of each of the layers of nitride materials in the first portion of the opening uncovered by the first liner is removed, the second portion of the first liner is removed, and a second portion of each of the layers of the nitride materials is removed in the second portion of the opening, wherein the second portion is less than the first portion.