Tiered Caching System for Storage Read Latency
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Solution Overview
Problem
Conventional storage systems face challenges in reducing read latency and cost due to limited cache memory and high expenses of 3D cross-point memory devices, while also requiring robust failure recovery mechanisms.
Innovation Solution
A tiered caching system is implemented using a short-term cache (e.g., DRAM) and a long-term cache (e.g., 3D cross-point memory) with primary and secondary storage controllers maintaining data structures to manage data location and redundancy, allowing efficient data retrieval and minimizing downtime in case of controller failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If cache memory size is increased to reduce read latency, then read latency is reduced, but cost increases due to limited cache memory resources
Solution Approach 1:
The cache memory is segmented into two distinct tiers: a first tier using DRAM for frequently accessed data and a second tier using 3D cross-point memory for less frequently accessed data. This segmentation allows the system to optimize read latency for hot data while using cheaper storage for cold data, resolving the contradiction between read latency and cache memory size.
Solution Approach 2:
The patent introduces a hierarchical dimension to the cache structure by organizing cache memory into multiple levels (DRAM tier and 3D cross-point memory tier) with different access speeds and costs. This dimensional organization allows the system to achieve low read latency for frequently accessed data while minimizing the total expensive cache memory required.
2Quantity of substance
If 3D cross-point memory is used extensively to reduce cost, then cost is reduced, but read latency increases due to slower access speed compared to DRAM
Solution Approach 1:
Different regions of the cache hierarchy are assigned different quality characteristics: the DRAM tier provides high-speed access for frequently accessed data, while the 3D cross-point memory tier provides higher capacity at lower cost for less frequently accessed data. This local quality differentiation resolves the contradiction between cache memory capacity and read latency.
Solution Approach 2:
The DRAM tier acts as an intermediary between the fast but small 3D cross-point memory and the slower but larger capacity storage. Frequently accessed data is kept in DRAM for rapid access, while the 3D cross-point memory provides extended capacity without directly impacting read latency for hot data.
3Device complexity
If data is stored in a single controller to simplify management, then device complexity is reduced, but reliability decreases due to potential single point of failure
Solution Approach 1:
The patent merges the functionality of multiple controllers into a unified tiered cache management system where both controllers cooperate to manage the cache hierarchy. This combining approach maintains simplified management while improving reliability through redundancy, as the system can continue operating with a single controller if needed.
Data Source
AI summary
A first read request for data stored at a non-volatile memory is received by a primary storage controller. The data is programmed from the non-volatile memory to a first cache of the primary storage controller, the first cache to store the data over a first time range. A second read request is received for the data. In response to receiving the second read request for the data, the data is programmed to a second cache to store the data over a second time range that is greater than the first time range. A notification is transmitted to a secondary storage controller, the notification including information associated with the programming of the data to the second cache.