Tiered Conductive Stack Layout for High-Density Vertical Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional vertical memory arrays face challenges in increasing memory density due to increased resistivity and decreased conductivity of conductive structures as the number of tiers increases, affecting the performance of memory cells.
Innovation Solution
A microelectronic device structure is formed with a first stack of alternating insulative and conductive structures, where a second stack with fewer tiers of conductive structures is formed over the first stack using physical vapor deposition, resulting in conductive structures with lower resistivity and improved conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of tiers of conductive structures increases to increase memory density, then memory density is improved, but resistivity of conductive structures increases and conductivity decreases
Solution Approach 1:
The patent applies local quality by forming a second stack structure with fewer tiers of conductive structures over the first stack structure. This creates a localized region with improved conductivity properties at the top portion of the memory device, where select gate structures are located, without compromising the overall high memory density achieved through the first stack structure.
Solution Approach 2:
The patent segments the conductive structures into two distinct stack structures: a first stack structure with a greater number of tiers for high memory density, and a second stack structure with fewer tiers for improved conductivity. This segmentation allows each region to be optimized for its specific function while working together as an integrated system.
2Quantity of substance
If the thickness of each tier decreases to increase the number of tiers within a given height, then memory density is improved, but processing difficulty increases
Solution Approach 1:
The patent divides the memory structure into two separate stack structures formed at different times and with different tier configurations. The first stack structure contains multiple thin tiers for high density, while the second stack structure contains fewer, potentially thicker tiers that are easier to process and align, thereby reducing overall processing difficulty.
Solution Approach 2:
The first stack structure with high memory density is formed first, establishing the foundation for high-capacity storage. Subsequently, the second stack structure is formed over it, allowing preliminary optimization of the high-density region before adding the second structure that requires different processing conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical conductivity of the conductive structures, improving the performance of memory cells and facilitating easier formation of memory strings with improved uniformity and alignment, thus addressing the limitations of conventional methods.
Implementation Method 1
a second stack with fewer tiers of conductive structures is formed over the first stack using physical vapor deposition
Data Source
AI summary
A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.