Tiered Contact Profile for Low-Resistance Semiconductor Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices scale down, contact resistance becomes a significant concern due to challenges in aligning smaller contacts, leading to unacceptably high resistance, and existing self-aligned contact methods increase complexity and production costs.
Innovation Solution
The formation of tiered-profile contacts using dual oxide layers with differential etch rates or sacrificial spacers to create a T-shaped design, where the top portion is wider than the bottom, minimizing misalignment and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned contact methods are used to address alignment challenges, then alignment precision is improved, but device complexity increases due to additional steps such as cap layer formation
Solution Approach 1:
The contact structure is divided into two distinct oxide layers with different etch rates, creating a segmented profile that enables self-alignment without requiring additional cap layers. The first oxide layer forms the lower contact portion while the second oxide layer forms the upper contact portion, allowing each layer to be etched at different rates to achieve the desired tiered profile.
Solution Approach 2:
Different oxide layers are used at different locations within the contact structure to achieve local optimization. The first oxide layer (with lower etch rate) is positioned at the bottom where precise alignment is critical, while the second oxide layer (with higher etch rate) is positioned at the top where broader alignment tolerance is acceptable, thereby improving overall alignment precision without increasing complexity.
2Area of moving object
If contact size is reduced to enable device scaling, then device density is improved, but contact resistance increases due to alignment difficulties
Solution Approach 1:
The contact structure employs an asymmetric tiered profile where the upper contact portion is wider than the lower contact portion. This asymmetric design allows the upper surface to provide a larger alignment target area, reducing misalignment risks and contact resistance, while the lower portion maintains the reduced footprint needed for device scaling and high density.
3Productivity
If contact-to-contact spacing is reduced to increase device density, then productivity is improved, but alignment precision deteriorates due to tapered contact profiles
Solution Approach 1:
The contact structure transitions from a conventional uniform cylindrical profile to a tiered profile with varying dimensions at different heights. The upper contact portion is designed with a larger diameter than the lower portion, creating a stepped three-dimensional structure. This dimensional variation allows closer contact spacing at the lower level while maintaining adequate alignment margins at the upper level, thereby enabling higher device density without sacrificing alignment precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The tiered-profile contacts reduce the risk of misalignment and contact resistance issues by providing a larger access area while maintaining a reduced footprint, enhancing the reliability and scalability of semiconductor devices.
Implementation Method 1
the second oxide layer has a greater etch rate than the first oxide layer
Implementation Method 2
removing the sacrificial spacers
Data Source
AI summary
Tiered-profile contacts for semiconductor devices and techniques for formation thereof are provided In one aspect, a method for forming tiered-profile contacts to a semiconductor device includes: depositing a first oxide layer over the semiconductor device; depositing a second oxide layer on the first oxide layer; patterning contact trenches through the first/second oxide layer down to the semiconductor device; isotropically etching a top portion of the contact trenches selective to a bottom portion of the contact trenches based on the second oxide layer having a greater etch rate than the first oxide layer to make the top portion of the contact trenches wider than the bottom portion; and filling the contact trenches with a contact metal(s) to form the tiered-profile contacts. Other methods to form tiered-profile contacts using sacrificial spacers as well as structures including the present tiered-profile contacts are also provided.