Tiered Copper Pillars for High-Aspect-Ratio Semiconductor Packaging
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Solution Overview
Problem
Conventional semiconductor package manufacturing techniques are limited by high costs, decreased reliability, and large package sizes due to difficulties in achieving high aspect ratios for copper pillars, as deeper holes become increasingly difficult to fill with conductive materials.
Innovation Solution
The method involves forming tiered pillars with a first tier having a larger width than the second tier, allowing for greater manufacturing tolerance and enabling higher aspect ratios by using copper plating processes to fill the holes, which are formed in resist layers, thereby overcoming the limitations of conventional single-tier pillar manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching and filling techniques are used to form copper pillars, then the manufacturing process is simple, but the aspect ratio is limited to about 2:1 due to difficulty in completely filling deeper holes with copper
Solution Approach 1:
The pillar structure is divided into multiple tiers with different widths. The first tier has a larger width to facilitate complete filling during the etching and copper deposition process, while the second tier has a smaller width to achieve the desired high aspect ratio. This segmentation allows the manufacturing process to succeed where a single-tier structure would fail.
2Length of moving object
If the depth of the etched hole is increased to achieve higher aspect ratios, then the pillar height increases, but it becomes increasingly difficult to completely fill the hole with copper
Solution Approach 1:
The pillar is segmented into a first tier with larger width and a second tier with smaller width. The first tier's larger width ensures complete copper filling during the deposition process, while the second tier achieves the desired height. This segmentation simultaneously increases pillar height and ensures filling reliability.
Solution Approach 2:
The first tier is formed with a larger width before the second tier is created. This preliminary action of establishing a wider base structure ensures that subsequent copper deposition processes can completely fill the pillar structure, preventing voids and ensuring reliability before the final high-aspect-ratio portion is formed.
3Manufacturing precision
If conventional single-tier pillar manufacturing is used, then the process is straightforward, but manufacturing tolerance is limited and aspect ratio cannot be significantly increased
Solution Approach 1:
The pillar is divided into multiple tiers with different widths, where the first tier has a larger width providing greater manufacturing tolerance, and the second tier has a smaller width achieving the desired aspect ratio. This segmentation improves manufacturing precision without requiring excessively complex processes.
Solution Approach 2:
Different portions of the pillar have different widths tailored to their specific functions. The first tier has a larger width optimized for manufacturing tolerance and complete filling, while the second tier has a smaller width optimized for achieving high aspect ratio. This local differentiation of properties optimizes both tolerance and aspect ratio.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the achievement of higher aspect ratios than conventional methods, reducing costs and improving reliability by ensuring complete filling of conductive materials in pillars, resulting in smaller and more efficient semiconductor packages.
Implementation Method 1
filling the hole with copper to form the copper pillar
Data Source
AI summary
A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.