Tiered ECC Metadata for Low Overhead Memory Integrity
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Solution Overview
Problem
Traditional memory integrity approaches suffer from significant performance overheads due to the need to load and verify cryptographic message authentication codes (MACs) for each memory access, which results in storage, performance, and bandwidth inefficiencies, and are limited by the availability of error correction code (ECC) bits in memory devices.
Innovation Solution
The Scalable Memory Integrity and Enhanced RAS (SMIRAS) architecture uses a tiered ECC organization, where ECC metadata is split into two tiers, with performance-critical ECC bits stored in ECC memory and secondary ECC metadata stored in sequestered memory, allowing for full error correction capabilities without additional performance overheads, and employs compression to optimize memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cryptographic message authentication codes (MACs) are associated with each dataline in memory for integrity protection, then memory integrity is improved, but performance overhead and storage overhead increase significantly
Solution Approach 1:
The patent segments the ECC metadata into two tiers: Tier 1 ECC metadata is stored in ECC memory alongside data lines for fast access, while Tier 2 ECC metadata is stored in sequestered memory. This segmentation allows the system to use only Tier 1 metadata for every memory access (maintaining performance), while Tier 2 metadata provides additional integrity protection (improving reliability). The segmentation resolves the contradiction by separating performance-critical operations from security-enhancing operations.
2Reliability
If cryptographic message authentication codes (MACs) are associated with each dataline in memory for integrity protection, then memory integrity is improved, but storage overhead increases
Solution Approach 1:
The patent makes the ECC metadata serve multiple functions: Tier 1 ECC metadata provides both error correction and integrity verification, while Tier 2 ECC metadata provides additional integrity protection. By making the ECC metadata multi-functional, the system eliminates the need for separate MAC storage, thereby reducing storage overhead while maintaining strong integrity protection.
3Reliability
If full error correction capabilities are implemented in memory, then reliability is improved, but device complexity and overhead increase
Solution Approach 1:
The patent segments ECC metadata into Tier 1 (stored in ECC memory) and Tier 2 (stored in sequestered memory). Tier 1 provides essential error correction for every data line, while Tier 2 provides additional correction capacity. This segmentation allows full error correction capabilities to be implemented without overwhelming device complexity, as the ECC memory handles the critical path operations while sequestered memory provides supplementary support.
Data Source
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AI summary
Techniques for Scalable Memory Integrity and Enhanced Reliability, Availability, and Serviceability (SMIRAS) based systems are described. A SMIRAS based system may be enabled to use an integrity-based metadata organization that stores data, metadata, and a first portion of ECC data together in memory and a second portion of ECC data in sequestered memory; or using a compression based organization that stores compressed data, compression metadata, and an second portion of ECC data as a cacheline.