Tiered ECC Memory Access for Weak Cell Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of maintaining error-free data storage in memory devices becomes increasingly difficult as technology scales down, particularly in the sub-25 nm regime, affecting both DRAM and its potential competitor STT-RAM, threatening the future growth of the semiconductor and computing industries.
Innovation Solution
A dynamically configurable error correction and detection system that utilizes tiered sets of weak memory cell locations to minimize storage redundancy, memory access latency, and energy consumption, allowing for error-tolerant memory operations without requiring changes to the memory chip circuit or interface design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM technology is scaled down to sub-25 nm regime to reduce bit cost, then memory capacity and integration density are improved, but data storage reliability deteriorates due to insufficient capacitor capacitance
Solution Approach 1:
The patent introduces an error correction code (ECC) system as an intermediary layer between the physical memory cells and the data storage function. This ECC system detects and corrects errors that occur in scaled-down memory cells, allowing the memory to maintain reliability even as individual cell capacitance becomes insufficient. The ECC acts as a mediator that compensates for the physical limitations of scaled memory cells.
Solution Approach 2:
The patent changes the operational parameters of the memory system by implementing dynamic voltage scaling and adaptive refresh rates based on detected error patterns. By adjusting these parameters in response to scaling effects, the system maintains data integrity despite reduced cell capacitance. The memory controller monitors and adjusts operating conditions to compensate for the physical constraints of sub-25 nm cells.
2Speed
If STT-RAM technology is adopted to replace DRAM, then memory speed and non-volatility are improved, but manufacturing cost and scalability deteriorate
Solution Approach 1:
The patent segments the memory system into distinct functional layers: a high-speed STT-RAM cache layer for frequently accessed data and a lower-cost DRAM or flash layer for bulk storage. This segmentation allows the system to leverage the speed advantages of STT-RAM where needed while avoiding the high manufacturing costs of implementing entire memory systems in STT-RAM. The segmented architecture enables gradual adoption and hybrid implementations.
3Reliability
If traditional error-free data storage constraints are maintained during scaling, then data integrity is preserved, but technology scaling progress is halted
Solution Approach 1:
The patent implements dynamic error correction strategies that adapt to the actual error rates observed in scaled memory devices. Rather than using static, overly conservative error correction codes that would reduce capacity, the system dynamically adjusts the level of error correction applied based on real-time monitoring of memory cell behavior. This dynamic approach allows aggressive scaling while maintaining data integrity through adaptive rather than rigid error protection.
Data Source
AI summary
A system and method of providing error tolerant memory access operations on a memory device. A method is disclosed including: providing location information of weak memory cells, wherein the location information includes addresses grouped into tiered sets, wherein each tiered set includes addresses having a number of weak memory cells; receiving a target address for a memory read operation; reading data from a virtual repair memory if the target address belongs to a first tiered set of addresses having a number of weak memory cells exceeding a threshold; and if the target address does not belong the first tiered set of addresses, reading data from the memory device and alternatively performing (a) an error correction and error detection (ECED) operation and (b) a target address look up operation, at different settings, until an error free result is obtained.