Tiered Error Correction for Homogeneous Memory Recovery
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Solution Overview
Problem
Existing memory systems face challenges in error recovery, particularly introducing fetch gaps and additional latency due to error correction mechanisms, which are not effectively addressed by current techniques.
Innovation Solution
A memory system with a tiered error correction and detection mechanism that includes a memory controller, error detection code, and error recovery mechanism, allowing for gapless fetches and efficient recovery operations across multiple memory channels using ECC and CRC, with programmable timers and counters for managing recovery processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code (ECC) protection is used across multiple memory channels, then reliability is improved, but productivity deteriorates due to reduced data transfer capacity
Solution Approach 1:
The patent segments error protection into two distinct layers: channel-level CRC for detection and line-level ECC for correction. This segmentation allows each layer to operate independently with optimized bit allocations, where CRC uses fewer bits for detection only, while ECC provides comprehensive correction capability, thereby improving overall reliability without proportionally reducing data transfer capacity.
Solution Approach 2:
The patent transitions from a single-dimension error protection approach to a two-dimensional hierarchical approach. The first dimension is channel-level detection using CRC, and the second dimension is line-level correction using ECC. This dimensional expansion allows the system to achieve both high reliability and maintained productivity by addressing errors at multiple levels of granularity.
2Reliability
If CRC is used on channel busses to detect errors, then reliability is improved through error detection, but productivity deteriorates due to required retries of failing operations
Solution Approach 1:
The patent applies preliminary error detection at the channel level using CRC before data is fully processed. By detecting errors early in the transmission process, the system can identify problematic channels and initiate recovery procedures before complete data corruption occurs, reducing the need for full operation retries and maintaining higher throughput.
Solution Approach 2:
The patent introduces an intermediary error recovery mechanism that sits between the CRC detection and the final data delivery. When CRC detects an error, the intermediary ECC mechanism attempts correction before data is discarded or requires full retry, thereby reducing retry frequency and maintaining productivity while preserving reliability.
3Reliability
If the entire line is delayed until all ECC is clean, then reliability is improved by ensuring error-free data, but productivity deteriorates due to increased latency on all lines
Solution Approach 1:
The patent applies local quality control by delaying only the specific quarter-line segments that contain errors, rather than delaying the entire 256-byte line. Each quarter-line is independently evaluated and delayed only if necessary, allowing error-free segments to proceed immediately. This localized approach maintains data integrity for corrected segments while minimizing latency impact on the overall fetch operation.
Solution Approach 2:
The patent applies partial action by selectively delaying only the portion of data that requires error correction, rather than delaying the complete data line. This partial delay approach ensures that error-free data segments are delivered promptly while problematic segments receive the necessary delay for correction, thereby maintaining reliability where needed without unnecessarily increasing latency for the entire operation.
4Productivity
If quarter lines are sent as fetched, then productivity is improved by reducing latency, but reliability deteriorates due to fetch gaps when errors occur
Solution Approach 1:
The patent implements dynamic error handling where the system adapts its behavior based on real-time error conditions. When no errors are detected in a quarter-line, data is sent immediately to maintain high throughput. When errors are detected, the system dynamically adjusts by delaying only the affected segment for correction, maintaining data continuity. This dynamic response allows the system to optimize between throughput and reliability based on actual operating conditions.
Solution Approach 2:
The patent ensures continuity of useful action by processing and sending error-free quarter-line segments without interruption while simultaneously handling errors in other segments. The error correction process for one segment does not halt the flow of valid data from other segments, maintaining continuous productive action throughout the fetch operation and preventing fetch gaps in the overall data stream.
Data Source
AI summary
Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels.