Tiered Gate Structure Fabrication for Parasitic Capacitance Reduction
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Solution Overview
Problem
T-gate structures face issues with parasitic capacitance, void formation during metal evaporation, and non-destructive gate length measurement, leading to reliability problems and process uniformity challenges in conventional fabrication processes.
Innovation Solution
A method involving the use of bilayer resist masks with dissimilar resist types for forming gate foot and gate head structures, allowing for non-destructive measurement of gate length and reducing parasitic capacitance through controlled e-beam exposure and lift-off processes, ensuring uniformity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If electron beam lithography is used to produce short gate length devices, then gate lengths less than 100 nanometers are achievable, but unwanted parasitic capacitance forms between the gate head and source/drain due to short gate foot height
Solution Approach 1:
The gate structure is segmented into two distinct parts: a narrow gate foot and a wider gate head. This segmentation allows the gate foot to maintain sufficient height for proper nitride coverage and reduced parasitic capacitance, while the gate head provides the necessary width for short gate length operation. The tiered configuration resolves the contradiction by separating the functional requirements of each gate region.
Solution Approach 2:
The gate structure transitions from a two-dimensional planar gate to a three-dimensional tiered structure with varying width along the vertical dimension. This dimensional change enables the gate foot to have different dimensions than the gate head, allowing optimization of both parasitic capacitance (through gate foot height) and gate length (through gate head width) simultaneously.
2Ease of manufacture
If the gate foot is formed in the same metallization step as the gate head, then fabrication is simplified, but voids form during metal evaporation causing reliability problems and potential gate structure breakage
Solution Approach 1:
The gate formation process is segmented into separate metallization steps: first the gate foot is formed, then the gate head is formed in a subsequent step. This process segmentation prevents void formation during metal evaporation by ensuring that metal is deposited on flat, stable surfaces rather than attempting to coat the complex tiered geometry in a single step, thereby resolving the reliability issue while maintaining reasonable fabrication complexity.
Solution Approach 2:
The gate foot is formed in advance before the gate head is deposited. This preliminary action creates a stable foundation that prevents void formation during subsequent metal evaporation steps. By preparing the lower gate structure first, the process ensures proper metal adhesion and eliminates the reliability problems associated with simultaneous formation.
3Ease of manufacture
If conventional fabrication processes are used, then manufacturing is straightforward, but gate length cannot be measured without destroying the device
Solution Approach 1:
The gate length is measured at an intermediate stage during fabrication, before the gate head is formed and before any destructive testing would be required. This preliminary measurement action allows non-destructive verification of gate length while maintaining the simplicity of conventional fabrication processes. The measurement is performed when the gate foot is exposed and accessible, enabling quality control without device destruction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables in situ measurement of gate length without device destruction, reduces parasitic capacitance, and improves process uniformity, resulting in more reliable and efficient T-gate structure fabrication.
Implementation Method 1
utilize electron beam lithography to produce short gate length devices
Implementation Method 2
The upper resist layer is exposed and developed using a first developer, and the lower resist layer is exposed and developed using a second developer
Implementation Method 3
Voids form during metal evaporation when some metal coats the side of the imaging layer mask causing the metal to self-mask
Implementation Method 4
A lift-off process is performed, removing at least a portion of the gate head mask
Data Source
AI summary
In one implementation, a method for fabricating a tiered structure is provided, which includes forming a source and a drain on a substrate with a gate formed therebetween. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped. A gate head mask is formed over the gate foot with the gate head mask exposing a top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.