Tiered IC Assembly with TSVs and Data Bridges
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Solution Overview
Problem
Conventional IC assemblies face challenges with low interconnect density between packages and printed circuit boards, leading to bandwidth bottlenecks, thermal expansion mismatches, and difficulties in providing electro-migration compliant power supply feeds, which limit the performance of high-performance electronic computing and communication systems.
Innovation Solution
The arrangement of disparate ICs in short vertical stacks with independent thermally-compliant connectors for power and ground, and laterally arranged data bridges with submicron metal interconnects for high-speed signaling, along with supplemental ICs using through-silicon vias for power and ground connections, to achieve similar interconnect density and signal integrity as on-chip connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional IC-package-board-package-IC configuration is used, then thermal management and power distribution are simplified, but interconnect density is low causing bandwidth bottlenecks
Solution Approach 1:
The patent transitions from a planar IC-package-board configuration to a three-dimensional stacked configuration with multiple tiers of ICs vertically arranged. This dimensional change enables significantly higher interconnect density through the use of through-silicon vias (TSVs) that penetrate vertically through multiple IC layers, allowing parallel data paths in the vertical dimension while maintaining thermal and power management capabilities through the tiered structure.
2Quantity of substance
If vertically stacked ICs are arranged to increase interconnect density, then bandwidth is improved, but heat removal from interior of stack becomes difficult
Solution Approach 1:
The patent divides the vertically stacked IC structure into multiple tiers, with each tier containing ICs that can be independently managed for thermal purposes. This segmentation allows heat generated in interior ICs to be distributed across multiple thermal zones, with each tier having its own thermal management strategy including proximity to heat sinks or thermal vias, preventing heat accumulation in the stack interior while maintaining high vertical interconnect density.
Solution Approach 2:
The patent introduces intermediate structures such as heat sinks, thermal vias, and thermally conductive materials positioned between tiers and at the base of the stack to facilitate heat removal. These intermediary thermal management components act as heat transfer pathways, conducting heat away from interior ICs through the vertical structure without compromising the high interconnect density achieved through the stacked configuration.
3Quantity of substance
If vertically stacked ICs are arranged to increase interconnect density, then bandwidth is improved, but providing electro-migration compliant power supply feeds becomes difficult
Solution Approach 1:
The patent utilizes the vertical dimension through through-silicon vias (TSVs) to provide power and ground connections between tiers, enabling electro-migration compliant power supply feeds to reach each IC in the stacked configuration. The vertical via structures provide low-impedance power paths that satisfy electro-migration requirements while delivering power to multiple tiers, solving the power distribution challenge inherent in vertical stacking without compromising interconnect density.
4Quantity of substance
If serialization-deserialization circuitry is added to increase off-chip data rates, then bandwidth is improved, but chip area, power consumption, and noise increase
Solution Approach 1:
The patent achieves high data rates by utilizing vertical stacking and TSV interconnects to create parallel data paths in the vertical dimension, eliminating the need for serialization-deserialization circuitry. Multiple data bits can be transmitted simultaneously through parallel vias between tiers, providing high bandwidth without requiring additional transistors, chip area, or power consumption associated with serial communication protocols.
Data Source
AI summary
A tiered integrated circuit (IC) assembly includes stacks of a limited number of ICs coupled to each other and arranged in a first direction across a base tier and a second tier. The base tier includes ICs and a data bridge. Each of the ICs includes a respective array of through silicon vias (TSVs) arranged in parallel with the first direction. The data bridge includes submicron metal interconnects (densely spaced electrical conductors) arranged in a plane that is substantially orthogonal to the first direction. The second tier is adjacent to the base tier and includes respective high-performance ICs different from the ICs of the base tier. The TSVs provide power and ground paths to the ICs in the second tier. In an example embodiment, the ICs in the second tier support one or more data bridges for connecting adjacent stacks.