Tiered Coherent Memory Address Decoding for Scalable Memory Support

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Solution Overview

Problem

Existing CPU designs face scalability issues and increased complexity due to a fixed number of system address decoder (SAD) rules, leading to higher memory latency and cost as they attempt to accommodate various memory technologies and modes, necessitating predictions of future memory usage models.

Innovation Solution

Implement a flexible provisioning of coherent memory address decoders with configurable tiers, each having a pool of address decoders and configuration registers, allowing for scalable and efficient handling of diverse memory types and technologies without predicting future needs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a fixed number of system address decoder rules are used to accommodate various memory technologies and modes, then the system can support multiple memory types, but the device complexity increases and scalability is limited

Engineering Contradiction:

Improvesupport for multiple memory typesVSAvoiddecoder rules complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic address decoding by replacing fixed SAD rules with a hierarchical tiered structure where decoders can be selectively enabled and configured at runtime. This allows the system to adapt to different memory technologies and modes without requiring a fixed large number of decoder rules, thereby reducing complexity while maintaining versatility.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The address decoding space is segmented into multiple hierarchical tiers (e.g., tier-0, tier-1, tier-2) with each tier handling specific aspects of address translation. This segmentation allows the system to support diverse memory types through modular configuration rather than requiring a monolithic fixed decoder structure, reducing overall complexity while preserving adaptability.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If more system address decoder rules are added to accommodate future memory technologies, then future memory usage models can be supported, but the manufacturing cost and complexity increase

Engineering Contradiction:

Improvefuture memory technology supportVSAvoidmanufacturing cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The hierarchical tiered decoder structure serves multiple functions: it can accommodate current memory technologies, support future memory types through configuration changes, and provide a scalable framework for evolving memory architectures. This universal structure eliminates the need to manufacture different decoder configurations for different memory technologies, reducing manufacturing costs while maintaining future support capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system supports future memory technologies by changing configuration parameters (such as enabling/disabling specific decoder tiers, modifying address mapping rules) rather than requiring hardware redesign or additional decoder rules. This parameter-based adaptability allows future memory support without increasing manufacturing complexity or cost.

Inventive Principle:

Principle #35Parameter changes

3Device complexity

If a fixed number of system address decoder rules are used, then the decoder structure is simple, but memory address decoding latency increases

Engineering Contradiction:

Improvedecoder structure simplicityVSAvoidaddress decoding latency

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

By segmenting the address decoding process into hierarchical tiers, the system can perform coarse filtering at upper tiers and fine-grained decoding at lower tiers only when needed. This segmented approach reduces the average decoding latency compared to a single fixed decoder structure, while maintaining structural simplicity through the organized tiered framework.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The hierarchical tiered structure performs preliminary address filtering and translation at upper tiers before passing addresses to lower tiers. This preliminary action reduces the workload and latency of subsequent decoding stages, achieving faster overall address decoding while keeping each individual tier relatively simple.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12487762B2Flexible provisioning of coherent memory address decoders in hardware

Publication Date: 2025.12.02 INTEL CORP

AI summary

Embodiments of apparatuses, methods, and systems for flexible provisioning of coherent memory address decoders in hardware are disclosed. In an embodiment, an apparatus includes a plurality of address decoders and a plurality of configuration storage locations. Each of the configuration storage locations corresponds to one of the plurality of address decoders to configure the corresponding one of the plurality of address decoders to decode based on a corresponding one of a plurality of decode rules. Each of the plurality of configuration storage locations is allocated to one of a plurality of memory tiers.